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Full-Text Articles in Engineering
One-Bit Algorithm Considerations For Sparse Pmcw Radar, Ethan Triplett
One-Bit Algorithm Considerations For Sparse Pmcw Radar, Ethan Triplett
Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research
Phase Modulated Continuous Wave (PMCW) radar an emerging technology for autonomous cars. It is more flexible than the current frequency modulated systems, offering better detection resolution, interference mitigation, and future development opportunities. The issue preventing PMCW adoption is the need for high sample-rate analog to digital converters (ADCs). Due to device limits, a large increase in cost and power consumption occurs for every added resolution bit for a given sampling rate. This thesis explores radar detection techniques for few-bit and 1-bit ADC measurements. 1-bit quantization typically results in poor amplitude estimation, which can limit detections if the target signals are …
Design And Simulation Of An 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter, Sumit K. Verma
Design And Simulation Of An 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter, Sumit K. Verma
Electrical Engineering Theses
The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage …
A Jittered-Sampling Correction Technique For Adcs, Jamiil A. Tourabaly
A Jittered-Sampling Correction Technique For Adcs, Jamiil A. Tourabaly
Theses: Doctorates and Masters
In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.