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Full-Text Articles in Physical Sciences and Mathematics
Packet Routing In Networks With Long Wires, Ronald I. Greenberg, Hyeong-Cheol Oh
Packet Routing In Networks With Long Wires, Ronald I. Greenberg, Hyeong-Cheol Oh
Computer Science: Faculty Publications and Other Works
In this paper, we examine the packet routing problem for networks with wires of differing length. We consider this problem in a network independent context, in which routing time is expressed in terms of "congestion" and "dilation" measures for a set of packet paths. We give, for any constant ϵ > 0, a randomized on-line algorithm for routing any set of Npackets in O((C lgϵ(Nd) + D lg(Nd))/lg lg(Nd)) time, where C is the maximum congestion and D is the length of the longest path, both taking wire delays into …
Finding Connected Components On A Scan Line Array Processor, Ronald I. Greenberg
Finding Connected Components On A Scan Line Array Processor, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This paper provides a new approach to labeling the connected components of an n x n image on a scan line array processor (comprised of n processing elements). Variations of this approach yield an algorithm guaranteed to complete in o(n lg n) time as well as algorithms likely to approach O(n) time for all or most images. The best previous solutions require using a more complicated architecture or require Omega(n lg n) time. We also show that on a restricted version of the architecture, any algorithm requires Omega(n lg n) time in the worst case.
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This paper shows that a fat-pyramid of area Θ(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more …
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
The paper provides an efficient method to find all feasible offsets for a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only for problems with no single-sided nets. When single-sided nets are included, the worst-case solution time increases from Theta(n) to Omega(n^2), where n is the number of nets. But, if the number of columns c is O(n), one can solve the problem in time O(n^{1.5}lg n ), which improves upon a `naive' O(cn) approach. As a corollary of this result, the same time bound suffices to find the optimal offset …
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We give algorithms to minimize density for channels with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, previous results for running time and space are improved by a factor of L/lg n and L , respectively, where L is the channel length and n is the number of terminals.