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Full-Text Articles in Physical Sciences and Mathematics
Increasing Bluetooth Low Energy Communication Efficiency By Presetting Protocol Parameters, Dusan Hatvani, Dominik Macko
Increasing Bluetooth Low Energy Communication Efficiency By Presetting Protocol Parameters, Dusan Hatvani, Dominik Macko
Turkish Journal of Electrical Engineering and Computer Sciences
Standard protocols are important regarding the compatibility of devices provided by different vendors. However, specific applications have various requirements and do not always need all features offered by standard protocols, making them inefficient. This paper focuses on standard Bluetooth Low Energy modifications, reducing control overhead for the intended healthcare application. Specifically, the connection establishment, device pairing, and connection parameter negotiations have been targeted. The simulation-based experiments showed over 20 times reduction of control-overhead time preceding a data transmission. It does not just directly increase the energy efficiency of communication; it also prolongs the time for sensor-based end devices to spend …
Hybrid Self-Controlled Precharge-Free Cam Design For Low Power And High Performance, V V Satyanarayana Satti, Sridevi Sriadibhatla
Hybrid Self-Controlled Precharge-Free Cam Design For Low Power And High Performance, V V Satyanarayana Satti, Sridevi Sriadibhatla
Turkish Journal of Electrical Engineering and Computer Sciences
Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a …
A Process-Tolerant Low-Power Adder Architecture For Image Processing Applications, Bharat Garg, G K. Sharma
A Process-Tolerant Low-Power Adder Architecture For Image Processing Applications, Bharat Garg, G K. Sharma
Turkish Journal of Electrical Engineering and Computer Sciences
The aggressive CMOS technology scaling in the sub-100-nm regime leads to highly challenging VLSI design due to the presence of unreliable components. The delay failures in arithmetic units are increasing rapidly due to the increased effect of process variation (PV) in scaled technology. This paper introduces a novel process-tolerant low-power adder (Prot-LA) architecture for error-tolerant applications. The proposed Prot-LA architecture segments the operands into two parts and computes addition of the upper parts in carry-propagate, whereas it computes the lower parts in a carry-free manner. In the Prot-LA, the number of bits in carry-propagate and carry-free additions can be reconfigured …