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Portland State University

Three-dimensional integrated circuits -- Design and construction

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Full-Text Articles in Physical Sciences and Mathematics

3d Fpga Cell Matrix By Self-Assembly, Jeffrey Udall Jan 2016

3d Fpga Cell Matrix By Self-Assembly, Jeffrey Udall

Undergraduate Research & Mentoring Program

Physical size limitations in miniaturizing two-dimensional (2D) transistors are becoming more difficult to overcome. In order to continue increasing the processing power of electronic circuits, new design paradigms are needed. Three-dimensional (3D) architectures provide a solution to this issue and are currently being implemented via wafer stacking. However, more significant gains in terms of packing and speed can be achieved by CMOS components with truly integrated 3D cellular architectures. One of these is the Cell Matrix, a self-configurable defect- and fault-tolerant architecture, which is ideally suited for ultra large-scale integration. For this project, we worked to expand the Cell Matrix …


Floorplan Design And Yield Enhancement Of 3-D Integrated Circuits, Rajeev Kumar Nain Jan 2011

Floorplan Design And Yield Enhancement Of 3-D Integrated Circuits, Rajeev Kumar Nain

Dissertations and Theses

We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit modules during the floorplanning stage. Thus it also bridges the existing gap between 3-D floorplanning and 3-D placement. To reduce the solution space of 3-D floorplanning which is known to be an NP-hard problem, we derive a set of feasibility conditions on the topological representation of a floorplan. In addition, we have designed a fast module packing algorithm that satisfies a set of constraints for placement-aware 3-D floorplanning. Furthermore, we have designed an efficient evolutionary algorithm …