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Physical Sciences and Mathematics Commons™
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Full-Text Articles in Physical Sciences and Mathematics
Syntactic Segmentation And Labeling Of Digitized Pages From Technical Journals, Mukkai Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan
Syntactic Segmentation And Labeling Of Digitized Pages From Technical Journals, Mukkai Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan
School of Computing: Faculty Publications
Alternating horizontal and vertical projection profiles are extracted from nested sub-blocks of scanned page images of technical documents. The thresholded profile strings are parsed using the compiler utilities Lex and Yacc. The significant document components are demarcated and identified by the recursive application of block grammars. Backtracking for error recovery and branch and bound for maximum-area labeling are implemented with Unix Shell programs. Results of the segmentation and labeling process are stored in a labeled X-Y tree. It is shown that families of technical documents that share the same layout conventions can be readily analyzed. More than 20 types of …
Accurate Computation Of Field Reject Ratio Based On Fault Latency, Dharamvir Das, Sharad C. Seth, Vishwani D. Agrawal
Accurate Computation Of Field Reject Ratio Based On Fault Latency, Dharamvir Das, Sharad C. Seth, Vishwani D. Agrawal
School of Computing: Faculty Publications
The field reject ratio, the fraction of defective devices that pass the acceptance test, is a measure of the quality of the tested product. Although the assessment of quality is important, an accurate measurement of the field reject ratio of tested VLSI chips is often not feasible. We show that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. We model the detection of a fault by an input test vector as a random event. However, we recognize that the detection of a fault may be delayed for …
Generating Tests For Delay Faults In Nonscan Circuits, Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
Generating Tests For Delay Faults In Nonscan Circuits, Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
School of Computing: Faculty Publications
This new method allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits. To test a given path, the authors augment the netlist model of the circuit with a logic block in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. The authors present results on benchmarks for nonscan and scan/hold modes of testing.