Physical Sciences and Mathematics Commons^™

Pairing Software-Managed Caching With Decay Techniques To Balance Reliability And Static Power In Next-Generation Caches, Kelly Shaw, Margaret Martonosi

Department of Math & Statistics Technical Report Series

Since array structures represent well over half the area and transistors on-chip, maintaining their ability to scale is crucial for overall technology scaling. Shrinking transistor sizes are resulting in increased probabilities of single events causing single- and multi-bit upsets which require adoption of more complex and power hungry error detection and correction codes (ECC) in hardware. At the same time, SRAM leakage energy is increasing partly due to technology trends and partly due to the increasing number of transistors present.

This paper proposes and evaluates methods of reducing the static power requirements of caches, while also maintaining high reliability. In …