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Full-Text Articles in Physical Sciences and Mathematics

A Sign-To-Speech Translation System, Koka Veera Raghava Rao Jan 1993

A Sign-To-Speech Translation System, Koka Veera Raghava Rao

Department of Computer Science and Engineering: Dissertations, Theses, and Student Research

This thesis describes sign-to-speech translation using neural networks. Sign language translation is an interesting but difficult problem for which neural network techniques seem promising because of their ability to adjust to the user's hand movements, which is not possible to do by most other techniques. However, even using neural networks and artificial sign languages, the translation is hard, and the best-known system, that of Fels & Hinton (1993), is capable of translating only 66 root words and 203 words including their conjugations. This research improves their results to 790 root signs and 2718 words including their conjugations while preserving a …


Clock Partitioning For Testability, Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal Jan 1993

Clock Partitioning For Testability, Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal

CSE Conference and Workshop Papers

An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented.


Accurate Computation Of Field Reject Ratio Based On Fault Latency, Dharamvir Das, Sharad C. Seth, Vishwani D. Agrawal Jan 1993

Accurate Computation Of Field Reject Ratio Based On Fault Latency, Dharamvir Das, Sharad C. Seth, Vishwani D. Agrawal

School of Computing: Faculty Publications

The field reject ratio, the fraction of defective devices that pass the acceptance test, is a measure of the quality of the tested product. Although the assessment of quality is important, an accurate measurement of the field reject ratio of tested VLSI chips is often not feasible. We show that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. We model the detection of a fault by an input test vector as a random event. However, we recognize that the detection of a fault may be delayed for …


Syntactic Segmentation And Labeling Of Digitized Pages From Technical Journals, Mukkai Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan Jan 1993

Syntactic Segmentation And Labeling Of Digitized Pages From Technical Journals, Mukkai Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan

School of Computing: Faculty Publications

Alternating horizontal and vertical projection profiles are extracted from nested sub-blocks of scanned page images of technical documents. The thresholded profile strings are parsed using the compiler utilities Lex and Yacc. The significant document components are demarcated and identified by the recursive application of block grammars. Backtracking for error recovery and branch and bound for maximum-area labeling are implemented with Unix Shell programs. Results of the segmentation and labeling process are stored in a labeled X-Y tree. It is shown that families of technical documents that share the same layout conventions can be readily analyzed. More than 20 types of …


Generating Tests For Delay Faults In Nonscan Circuits, Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth Jan 1993

Generating Tests For Delay Faults In Nonscan Circuits, Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth

School of Computing: Faculty Publications

This new method allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits. To test a given path, the authors augment the netlist model of the circuit with a logic block in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. The authors present results on benchmarks for nonscan and scan/hold modes of testing.