Physical Sciences and Mathematics Commons^™

A Synthesis For Testability Scheme For Finite State Machines Using Clock Control, Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth

School of Computing: Faculty Publications

A new method is proposed for improving the testability of a finite state machine (FSM) during its synthesis. The method exploits clock control to enhance the controllability and observability of machine states. With clock control it is possible to add new state transitions during testing. Therefore, it is easier to navigate between states in the resulting test machine. Unlike prior work, where clock control is added to the circuit as a postdesign step, here, clock control is considered in conjunction with a symbolic scheme for encoding the states of the FSM. The encoding is shown to result in significant reductions …