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Improving Processor Efficiency By Statically Pipelining Instructions, Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David Whalley, Magnus Sjalander, Gary Tyson
Improving Processor Efficiency By Statically Pipelining Instructions, Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David Whalley, Magnus Sjalander, Gary Tyson
Gang-Ryung Uh
A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that …