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Full-Text Articles in Physical Sciences and Mathematics
Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held
Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held
Electronic Thesis and Dissertation Repository
Efficient and accurate tomographic image reconstruction has been an intensive topic of research due to the increasing everyday usage in areas such as radiology, biology, and materials science. Computed tomography (CT) scans are used to analyze internal structures through capture of x-ray images. Cone-beam CT scans project a cone-shaped x-ray to capture 2D image data from a single focal point, rotating around the object. CT scans are prone to multiple artifacts, including motion blur, streaks, and pixel irregularities, therefore must be run through image reconstruction software to reduce visual artifacts. The most common algorithm used is the Feldkamp, Davis, and …
High Dynamic Performance Of A Bldc Motor With A Front End Converter Using An Fpga Based Controller For Electric Vehicle Application, Praveen Yadav, Rajesh Poola, Khaja Najumudeen
High Dynamic Performance Of A Bldc Motor With A Front End Converter Using An Fpga Based Controller For Electric Vehicle Application, Praveen Yadav, Rajesh Poola, Khaja Najumudeen
Turkish Journal of Electrical Engineering and Computer Sciences
This paper focus on a novel operation of a brushless dc (BLDC) motor fed by a proportional integral (PI) controlled buck--boost converter supplemented with a battery to provide the required power to drive the BLDC motor. The operational characteristics of the proposed BLDC motor drive system for constant as well as step changes in dc link voltage of a front end converter controlled by a Xilinx System Generator (XSG) based PI controller for two quadrant operations are derived. Thus a field programmable gate array (FPGA) based PI controller manages the energy flow through the battery and the front end converter. …
Fpga Implementation Of A Hevc Deblocking Filter For Fast Processing Of Super High Resolution Applications, Awais Khan, Gulistan Raja
Fpga Implementation Of A Hevc Deblocking Filter For Fast Processing Of Super High Resolution Applications, Awais Khan, Gulistan Raja
Turkish Journal of Electrical Engineering and Computer Sciences
This paper proposes the architecture of a deblocking filter (DBF) that removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). A parallel architecture for both normal and strong filtering modes of HEVC is proposed. Distributed memories and two data paths increase the parallelism and make the architecture more efficient. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real time to compute 4K UHD video at 30 fps by using 46.65 million clocks with total equivalent gate count of 46K. The maximum delay time for output to come after taking input for …
Implementation Of A Modified Svpwm-Based Three-Phase Inverter With Reduced Switches Using A Single Dc Source For A Grid-Connected Pv System, Venkatesan Mani, Rajeswari Ramachandran, Deverajan Nanjundappan
Implementation Of A Modified Svpwm-Based Three-Phase Inverter With Reduced Switches Using A Single Dc Source For A Grid-Connected Pv System, Venkatesan Mani, Rajeswari Ramachandran, Deverajan Nanjundappan
Turkish Journal of Electrical Engineering and Computer Sciences
No abstract provided.
An Alternative Carry-Save Arithmetic For New Generation Field Programmable Gate Arrays, Uğur Çi̇ni̇, Mustafa Aktan, Avni̇ Morgül
An Alternative Carry-Save Arithmetic For New Generation Field Programmable Gate Arrays, Uğur Çi̇ni̇, Mustafa Aktan, Avni̇ Morgül
Turkish Journal of Electrical Engineering and Computer Sciences
In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than …