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A 10-Gb/S Single-Loop Half-Rate Dll-Based Clock And Data Recovery Circuit For Forwarded-Clock Wireline Transceivers, Abdallah K. Mohamed, Sameh A. Ibrahim, Mohy Eldin A. Abo-Elsoud
A 10-Gb/S Single-Loop Half-Rate Dll-Based Clock And Data Recovery Circuit For Forwarded-Clock Wireline Transceivers, Abdallah K. Mohamed, Sameh A. Ibrahim, Mohy Eldin A. Abo-Elsoud
Mansoura Engineering Journal
This paper introduces a 10-Gb/s single-loop, half-rate delay-locked loop (DLL)-based clock and data recovery (CDR) circuit for forwarded-clock (FC) wireline transceivers. The proposed CDR employs a differential ring oscillator (RO) with sub-feedback loops structure for multi-phase clock generation with a single-loop operation. An Alexander phase detector utilizing a flip-flop based on an improved true single-phase clock (TSPC) logic with split outputs is adopted. The proposed DLL-based CDR is an optimized solution in terms of area and power for FC wireline transceivers. The recovered clock exhibits an RMS jitter of 590 fs and a peak-to-peak jitter of 3.8 ps. The circuit …