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Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …
A Parallel Processing Architecture For Dqdb Protocol Implementation, Nilesh Vinubhai Gandhi
A Parallel Processing Architecture For Dqdb Protocol Implementation, Nilesh Vinubhai Gandhi
Theses
The high bandwidth transmission links, which have been provided by the advances of Fiber Optics Technology, reduce drastically the packet transmission times and place new demands on the nodal protocol processing. Segmentation and reassembly of packets, computation of checksums, introduction of source and destination addresses, etc., must be performed extremely fast in order to prevent node processing from becoming the bottleneck of the transmission. Parallel processing enables the execution of the previous tasks on multiple packets simultaneously and therefore has the potential of addressing the issue of fast node processing successfully. In this thesis we focus on the Medium Access …