Engineering Commons^™

Hardware Design For Jpeg And A Comparative Study Of Jpeg And Mpeg Image Compression Algorithms, Aravind Soundararajan

Theses

The complete PC-based hardware design along with the initialization and control software of the JPEG algorithm is presented in this thesis. The hardware could run in real-time to compress, decompress and display still frame images. LSI Logic JPEG chipset was used in the design. This is a dedicated chipset for the JPEG compression algorithm.

A simulation software was used for studying the performance of MPEG video compression algorithm. Various video test sequences were compressed through the codec simulation software and the resulting rate-distortion performance was calculated. These are compared with the performance of JPEG based image sequence compressor.

It is …

A Parallel Processing Architecture For Dqdb Protocol Implementation, Nilesh Vinubhai Gandhi

Theses

The high bandwidth transmission links, which have been provided by the advances of Fiber Optics Technology, reduce drastically the packet transmission times and place new demands on the nodal protocol processing. Segmentation and reassembly of packets, computation of checksums, introduction of source and destination addresses, etc., must be performed extremely fast in order to prevent node processing from becoming the bottleneck of the transmission. Parallel processing enables the execution of the previous tasks on multiple packets simultaneously and therefore has the potential of addressing the issue of fast node processing successfully. In this thesis we focus on the Medium Access …