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Full-Text Articles in Engineering
Low-Power Redundant-Transition-Free Tspc Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer, Zisong Wang, Peiyi Zhao, Tom Springer, Congyi Zhu, Jaccob Mau, Andrew Wells, Yinshui Xia, Lingli Wang
Low-Power Redundant-Transition-Free Tspc Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer, Zisong Wang, Peiyi Zhao, Tom Springer, Congyi Zhu, Jaccob Mau, Andrew Wells, Yinshui Xia, Lingli Wang
Engineering Faculty Articles and Research
In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% …
Clock Gating Flip-Flop Using Embedded Xor Circuitry, Peiyi Zhao, William Cortes, Congyi Zhu, Tom Springer
Clock Gating Flip-Flop Using Embedded Xor Circuitry, Peiyi Zhao, William Cortes, Congyi Zhu, Tom Springer
Engineering Faculty Articles and Research
Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior state-of-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.