Engineering Commons^™

Class F And Inverse Class F Power Amplifier Subject To Electrical Stress Effect, Giji Skaria

Electronic Theses and Dissertations

This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-toSource voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18µm CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. …

Cmos Rf Cituits Sic] Variability And Reliability Resilient Design, Modeling, And Simulation, Yidong Liu

Electronic Theses and Dissertations

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design …

Study Of Esd Effects On Rf Power Amplifiers, Raju, Divya Narasimha

Electronic Theses and Dissertations

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on …

High Linearity 5.8 Ghz Power Amplifier With An Internal Linearizer, Yiheng Wang

Electronic Theses and Dissertations

A 5.8 GHz RF Power Amplifier (PA) is designed and fabricated in this work, which has very high linearity through a built-in linearizer. The PA is designed, post-layout simulated by Agilent Advanced Design System (ADS) software and fabricated by Win-Semiconductors 0.15µm pHEMT process technology. The post-layout simulation results illustrate the power amplifier can obtained an output power of 23.98 dBm, a power gain of 32.28 dB and a power added efficiency (PAE) of 29% at saturation region, the 3rd intermodulation distortion (IMD3) of -37.7 dBc at 0 dBm input power is attained when operation frequency is 5.8 GHz. We finally …

Design And Analysis Of Class Ab Rf Power Amplifier For Wireless Communication Applications, Mohamed El-Dakroury

Retrospective Theses and Dissertations

The Power Amplifier is the most power-consulting block among the building blocks of RF transceivers. It is still a difficult problem to design power amplifiers, especially for linear, low voltage operation. Until now power amplifiers for wireless applications is being produced almost in GaAs processes with some exceptions in LDMOS, Si BJT, and SiGe HBT. The submicron CMOS processes for power amplifiers are under research focus since CMOS offers integration for power amplifier with rest of the transceivers blocks due to its high yield. Also CMOS process is cheap.

This thesis report details the design process of a class AB …

The Design And Development Of A Power Hybrid, Robert J. Albert

Retrospective Theses and Dissertations

This report discusses the design, development and the fabrication of a power hybrid. Foldback current limiting which is self reseting is used whereby withstanding indefinitely a short circuit. Thermal design considerations and thermal analysis are described as well as stability analysis. The maximum current capability of this design is four amperes and forty watts can be dissipated in the power transistors over a wide range of temperatures.