Engineering Commons^™

Memristive Architectures And Algorithms For Approximate Graph-Based Inference, Mohammad M.A. Taha

Dissertations and Theses

The goal of this thesis is to design fast, low-power, robust graph-based inference systems. Our approach to this is by using (1) in-memory computing, (2) approximate computing principles, and (3) memristive devices.

This work is motivated by the fact that conventional von Neumann architectures are not efficient for inference applications, mainly due to the data transfer bottleneck. Adding cache memories and using GPUs is a remedy, however, does not eliminate this bottleneck. In-memory computing is an alternative approach that performs all computations inside the memory, thus eliminating the data transfer bottleneck.

The memristor, which is a passive two-terminal device, is …

New Approaches For Memristive Logic Computations, Muayad Jaafar Aljafar

Dissertations and Theses

Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore's Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new …

Architectures And Algorithms For Intrinsic Computation With Memristive Devices, Jens Bürger

Dissertations and Theses

Neuromorphic engineering is the research field dedicated to the study and design of brain-inspired hardware and software tools. Recent advances in emerging nanoelectronics promote the implementation of synaptic connections based on memristive devices. Their non-volatile modifiable conductance was shown to exhibit the synaptic properties often used in connecting and training neural layers. With their nanoscale size and non-volatile memory property, they promise a next step in designing more area and energy efficient neuromorphic hardware.

My research deals with the challenges of harnessing memristive device properties that go beyond the behaviors utilized for synaptic weight storage. Based on devices that exhibit …

Complete Design Methodology Of A Massively Parallel And Pipelined Memristive Stateful Imply Logic Based Reconfigurable Architecture, Kamela Choudhury Rahman

Dissertations and Theses

Continued dimensional scaling of CMOS processes is approaching fundamental limits and therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks that can be easily reconfigured. This research involves the design of a memristor-based massively parallel datapath for various applications, specifically SIMD (Single Instruction Multiple Data) like architecture, and parallel pipelines. The dissertation develops a new model of massively parallel memristor-CMOS hybrid datapath architectures at …

The Design Of A Simple, Spiking Sparse Coding Algorithm For Memristive Hardware, Walt Woods

Dissertations and Theses

Calculating a sparse code for signals with high dimensionality, such as high-resolution images, takes substantial time to compute on a traditional computer architecture. Memristors present the opportunity to combine storage and computing elements into a single, compact device, drastically reducing the area required to perform these calculations. This work focused on the analysis of two existing sparse coding architectures, one of which utilizes memristors, as well as the design of a new, third architecture that employs a memristive crossbar. These architectures implement either a non-spiking or spiking variety of sparse coding based on the Locally Competitive Algorithm (LCA) introduced by …