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Missouri University of Science and Technology
<p>Asynchronous circuits -- Testing<br />Field programmable gate arrays</p>
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Design For Test Techniques For Asynchronous Ncl Designs And Fpgas, Sindhu Kakarla
Design For Test Techniques For Asynchronous Ncl Designs And Fpgas, Sindhu Kakarla
Masters Theses
"Testing of an electronic chip is an important step in the design process, as it can detect faults and ensure reliability. Design for Test (DFT) methods are used to modify existing designs to enable their testing by Automatic Test Pattern Generators. This thesis focuses on developing testing techniques for design automation of NULL Conventional Logic (NCL) circuits and for detection of capacitive crosstalk effects in Field Programmable Gate Arrays (FPGAs).
A novel technique is developed for testing asynchronous NCL designs aimed at good fault coverage with acceptable gate overhead. The technique focuses on testing stuck-at-faults in the internal feedback paths …