Open Access. Powered by Scholars. Published by Universities.®

Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

Air Force Institute of Technology

Computer Engineering

Algorithms

Publication Year

Articles 1 - 7 of 7

Full-Text Articles in Engineering

Constellation Design Of Geosynchronous Navigation Satellites Which Maximizes Availability And Accuracy Over A Specified Region Of The Earth, Halil Ibrahim Ozdemir Mar 2008

Constellation Design Of Geosynchronous Navigation Satellites Which Maximizes Availability And Accuracy Over A Specified Region Of The Earth, Halil Ibrahim Ozdemir

Theses and Dissertations

Currently, there are four Global Navigation Satellite Systems (GNSS) either being developed or in existence-GPS, GLONASS, Compass, and Galileo. Additionally, there are several Regional Navigation Satellite Systems (RNSS) planned or in existence, as well as numerous augmentation systems (which require a GNSS for operation). It can be anticipated that there will be interest in developing additional independent regional navigation satellite systems to cover areas of interest to particular countries or regions, who want to have their own system. In this paper, a genetic algorithm is used in an effort to determine near-optimal RNSS constellations. First, a cost function is setup, …


Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley Mar 2008

Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley

Theses and Dissertations

There is a need to expedite the process of designing military hardware to stay ahead of the adversary. The core of this project was to build reusable, synthesizeable libraries to make this a possibility. In order to build these libraries, Matlab® commands and functions, such as Conv2, Round, Floor, Pinv, etc., had to be converted into reusable VHDL modules. These modules make up reusable libraries for the Mission Specific Process (MSP) which will support AFRL/RY. The MSP allows the VLSI design process to be completed in a mere matter of days or months using an FPGA or ASIC design, as …


Performance Analysis Of A Dynamic Bandwidth Allocation Algorithm In A Circuit-Switched Communications Network, Timothy M. Schwamb Mar 2002

Performance Analysis Of A Dynamic Bandwidth Allocation Algorithm In A Circuit-Switched Communications Network, Timothy M. Schwamb

Theses and Dissertations

Military communications networks typically employ a gateway multiplexer to aggregate all communications traffic onto a single link. These multiplexers typically use a static bandwidth allocation method via time-division multiplexing (TDM). Inefficiencies occur when a high-bandwidth circuit, e.g., a video teleconferencing circuit, is relatively inactive rendering a considerable portion of the aggregate bandwidth wasted while inactive. Dynamic bandwidth allocation (DBA) reclaims unused bandwidth from circuits with low utilization and reallocates it to circuits with higher utilization without adversely affecting queuing delay. The proposed DBA algorithm developed here measures instantaneous utilization by counting frames arriving during the transmission time of a single …


A Reconfigurable Superscalar Architecture, Christopher B. Mayer Dec 1997

A Reconfigurable Superscalar Architecture, Christopher B. Mayer

Theses and Dissertations

The invention of the Field Programmable Gate Array (FPGA) has led to a number of interesting developments. One is the idea of providing custom hardware support for applications running on a computer. These reconfigurable computers have been shown to decrease the execution time for some applications. Based on past results, attention has subsequently turned to using reconfigurable computing in general-purpose computers (e.g. desktop and workstation environments). This thesis develops a design for just such a computer. The design, FPGADLX, is based on a hypothetical superscalar computer running the DLX instruction set and is generic enough in principle to be adapted …


Modeling And Simulation Support For Parallel Algorithms In A High-Speed Network, Dustin E. Yates Dec 1997

Modeling And Simulation Support For Parallel Algorithms In A High-Speed Network, Dustin E. Yates

Theses and Dissertations

This thesis investigates the ability of a simulation model to compare and contrast parallel processing algorithms in a high-speed network. The model extends existing modeling, analysis, and comparison of parallel algorithms by providing graphics based components that facilitate the measurement of system resources. Simulation components are based on the Myrinet local area network standard. The models provide seven different topologies to contrast the performance of five variations of Fast Fourier Transform (FFT) algorithms. Furthermore, the models were implemented using a commercially developed product that facilitates the testing of additional topologies and the investigation of hardware variations. Accurate comparisons are statistically …


A Mammographic Registration Method Based On Optical Flow And Multiresolution Computing, Kevin A. Lee Dec 1997

A Mammographic Registration Method Based On Optical Flow And Multiresolution Computing, Kevin A. Lee

Theses and Dissertations

Mammography is a potent weapon in the fight against Breast Cancer, due in large part to its widespread availability and low cost. Despite the fact that mammography can detect small lesions as early as two years before they become palpable on physical exam, between 10 and 30 percent of cancerous lesions go undetected during evaluation by the radiologist. One approach to improving detection rates involves comparing mammograms of the same breast from successive years. Since most forms of breast cancer develop slowly, multiple view techniques might be able to detect subtle changes indicative of cancerous growth. This thesis proposes a …


Fpga Processor Implementation For The Forward Kinematics Of The Umdh, Steven M. Parmley Dec 1997

Fpga Processor Implementation For The Forward Kinematics Of The Umdh, Steven M. Parmley

Theses and Dissertations

The focus of this research was on the implementation of a forward kinematic algorithm for the Utah MIT Dexterous Hand (UMDH). Specifically, the algorithm was synthesized from mathematical models onto a Field Programmable Gate Array (FPGA) processor. This approach is different from the classical, general purpose microprocessor design where all robotic controller functions including forward Kinematics are executed serially from a compiled programming language such as C. The compiled code and subsequent real time operating system must be stored on some form of nonvolatile memory, typically magnetic media such as a fixed or hard disk drive, along with other computer …