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Articles 1 - 7 of 7
Full-Text Articles in Engineering
Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj
Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj
Masters Theses 1911 - February 2014
Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance …
Approaches To Multiprocessor Error Recovery Using An On-Chip Interconnect Subsystem, Ramakrishna P. Vadlamani
Approaches To Multiprocessor Error Recovery Using An On-Chip Interconnect Subsystem, Ramakrishna P. Vadlamani
Masters Theses 1911 - February 2014
For future multicores, a dedicated interconnect subsystem for on-chip monitors was found to be highly beneficial in terms of scalability, performance and area. In this thesis, such a monitor network (MNoC) is used for multicores to support selective error identification and recovery and maintain target chip reliability in the context of dynamic voltage and frequency scaling (DVFS). A selective shared memory multiprocessor recovery is performed using MNoC in which, when an error is detected, only the group of processors sharing an application with the affected processors are recovered. Although the use of DVFS in contemporary multicores provides significant protection from …
Evaluating A New Mac For Current And Next Generation Rfid, Serge Zhilyaev
Evaluating A New Mac For Current And Next Generation Rfid, Serge Zhilyaev
Masters Theses 1911 - February 2014
We evaluate SQUASH, a new MAC for RFID, in hardware and software. A smaller hardware design for SQUASH is proposed which also reduces latency. Area and latency in hardware are reduced further with a new variant we call permuted SQUASH. We explore SQUASH on embedded microprocessors and propose a method to choose the optimal partial product ordering to reduce latency.
Scalable, Memory-Intensive Scientific Computing On Field Programmable Gate Arrays, Salma Mirza
Scalable, Memory-Intensive Scientific Computing On Field Programmable Gate Arrays, Salma Mirza
Masters Theses 1911 - February 2014
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for many scientific computing problems. This is due to the memory bottleneck that is encountered with large arrays that must be stored in dynamic RAM. A system of FPGAs, with a large enough memory bandwidth, and clocked at only hundreds of MHz can outperform a CPU clocked at GHz in terms of floating point performance. An FPGA core designed for a target performance that does not unnecessarily exceed the memory imposed bottleneck can then be distributed, along …
Fast Parameter-Space Sweep Of Wideband Electromagnetic Systems Using Bt-Pod, Wei Wang
Fast Parameter-Space Sweep Of Wideband Electromagnetic Systems Using Bt-Pod, Wei Wang
Masters Theses 1911 - February 2014
Modeling and design of high frequency electronic systems such as antennas and microwave devices require the rigorous numerical solution of Maxwell’s equa- tions. The frequency-domain (time-harmonic) tangential vector finite element method (TVFEM) for Maxwell equations results in a second-order dynamical electromagnetic model that must be repeatedly solved for multiple frequencies, excitation or material parameters each design loop. This leads to extremely long design turnaround that often is not optimal. This work will propose an accurate, error controllable and ef- ficient multi-parametric model order reduction scheme that significantly accelerate these parameters sweep. At the core of this work is the proper …
Optical Lithography Simulation Using Wavelet Transform, Rance Rodrigues
Optical Lithography Simulation Using Wavelet Transform, Rance Rodrigues
Masters Theses 1911 - February 2014
Optical lithography is an indispensible step in the process flow of Design for Manufacturability (DFM). Optical lithography simulation is a compute intensive task and simulation performance, or lack thereof can be a determining factor in time to market. Thus, the efficiency of lithography simulation is of paramount importance. Coherent decomposition is a popular simulation technique for aerial imaging simulation. In this thesis, we propose an approximate simulation technique based on the 2D wavelet transform and use a number of optimization methods to further improve polygon edge detection. Results show that the proposed method suffers from an average error of less …
Efficient Modeling Techniques For Time-Dependent Quantum System With Applications To Carbon Nanotubes, Zuojing Chen
Efficient Modeling Techniques For Time-Dependent Quantum System With Applications To Carbon Nanotubes, Zuojing Chen
Masters Theses 1911 - February 2014
The famous Moore's law states: Since the invention of the integrated circuit, the number of transistors that can be placed on an integrated circuit has increased exponentially, doubling approximately every two years. As a result of the downscaling of the size of the transistor, quantum effects have become increasingly important while affecting significantly the device performances. Nowadays, at the nanometer scale, inter-atomic interactions and quantum mechanical properties need to be studied extensively. Device and material simulations are important to achieve these goals because they are flexible and less expensive than experiments. They are also important for designing and characterizing new …