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Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj
Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj
Masters Theses 1911 - February 2014
Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance …
Evaluating A New Mac For Current And Next Generation Rfid, Serge Zhilyaev
Evaluating A New Mac For Current And Next Generation Rfid, Serge Zhilyaev
Masters Theses 1911 - February 2014
We evaluate SQUASH, a new MAC for RFID, in hardware and software. A smaller hardware design for SQUASH is proposed which also reduces latency. Area and latency in hardware are reduced further with a new variant we call permuted SQUASH. We explore SQUASH on embedded microprocessors and propose a method to choose the optimal partial product ordering to reduce latency.