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Full-Text Articles in Engineering
Approaches To Multiprocessor Error Recovery Using An On-Chip Interconnect Subsystem, Ramakrishna P. Vadlamani
Approaches To Multiprocessor Error Recovery Using An On-Chip Interconnect Subsystem, Ramakrishna P. Vadlamani
Masters Theses 1911 - February 2014
For future multicores, a dedicated interconnect subsystem for on-chip monitors was found to be highly beneficial in terms of scalability, performance and area. In this thesis, such a monitor network (MNoC) is used for multicores to support selective error identification and recovery and maintain target chip reliability in the context of dynamic voltage and frequency scaling (DVFS). A selective shared memory multiprocessor recovery is performed using MNoC in which, when an error is detected, only the group of processors sharing an application with the affected processors are recovered. Although the use of DVFS in contemporary multicores provides significant protection from …
Scalable, Memory-Intensive Scientific Computing On Field Programmable Gate Arrays, Salma Mirza
Scalable, Memory-Intensive Scientific Computing On Field Programmable Gate Arrays, Salma Mirza
Masters Theses 1911 - February 2014
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for many scientific computing problems. This is due to the memory bottleneck that is encountered with large arrays that must be stored in dynamic RAM. A system of FPGAs, with a large enough memory bandwidth, and clocked at only hundreds of MHz can outperform a CPU clocked at GHz in terms of floating point performance. An FPGA core designed for a target performance that does not unnecessarily exceed the memory imposed bottleneck can then be distributed, along …