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Understanding Timing Error Characteristics From Overclocked Systolic Multiply-Accumulate Arrays In Fpgas, Andrew S. Chamberlin
Understanding Timing Error Characteristics From Overclocked Systolic Multiply-Accumulate Arrays In Fpgas, Andrew S. Chamberlin
All Graduate Theses and Dissertations, Fall 2023 to Present
Artificial Intelligence (AI) is one of the biggest fields of research for computer hardware right now. Hardware accelerators are chips (such as graphics cards) that are purpose built to be the best at a specific type of operation. AI hardware accelerators are a growing field of research. Part of hardware in general is a digital clock that controls the pace at which computations occur. If this clock runs too quickly, the hardware won't have enough time to finish its computation. We call that a timing error. This paper focuses on studying the characteristics of timing errors in a small custom …
Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays In Fpgas, Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays In Fpgas, Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply–Accumulate Array (SMA) as its computational brain. In this paper, we investigate the faulty output characterization of an SMA in a real silicon FPGA board. Experiments were run on a single Zybo Z7-20 board to control for process variation at nominal voltage and in small batches to control for temperature. The FPGA is rated up to 800 MHz in the data sheet due to the max frequency of the PLL, but the …