Low Cost Dynamic Architecture Adaptation Schemes For Drowsy Cache Management, Nitin Prakash

Masters Theses 1911 - February 2014

Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost dynamic architecture adaptation scheme to save leakage power in caches. This design uses voltage scaling to implement drowsy caches. The importance of a dynamic scheme for managing drowsy caches, arises from the fact that not only does cache behavior change from one application to the next, but also during different phases of execution within the same application. We discuss various implementations of our scheme that provide a tradeoff between granularity of control and design complexity. …

N3asics: Designing Nanofabrics With Fine-Grained Cmos Integration, Pavan Panchapakeshan

Masters Theses 1911 - February 2014

Nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. These fabrics employ unconventional manufacturing techniques like Nano-imprint lithography or Super-lattice Nanowire Pattern Transfer to produce ultra-dense nano-structures. However, one key challenge that has received limited attention is the interfacing of unconventional/self-assembly based approaches with conventional CMOS manufacturing to build integrated systems.

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules to build a reliable nanowire-CMOS 3-D integrated fabric called N³ASICs with no new manufacturing constraints. In N³ASICs …

A Study Of The Impact Of Computational Delays In Missile Interception Systems, Ye Xu

Masters Theses 1911 - February 2014

Most publications discussing missile interception systems assume a zero computer response time. This thesis studies the impact of computer response time on single-missile single-target and multiple- missile multiple-target systems. Simulation results for the final miss distance as the computer response time increases are presented. A simple online cooperative adjustment model for multiple-missile multiple-target system is created for the purpose of studying the computer delay effect.

A Real Time Web Based Electronic Triage, Resource Allocation And Hospital Dispatch System For Emergency Response, Venkata Srihari Inampudi

Masters Theses 1911 - February 2014

Disasters are characterized by large numbers of victims and required resources, overwhelming the available resources. Disaster response involves various entities like Incident Commanders, dispatch centers, emergency operations centers, area command and hospitals. An effective emergency response system should facilitate coordination between these various entities. Victim triage, emergency resource allocation and victim dispatch to hospitals form an important part of an emergency response system. In this present research effort, an emergency response system with the aforementioned components is developed.

Triage is the process of prioritizing mass casualty victims based on severity of injuries. The system presented in this thesis is a …

A Real Time Indoor Navigation And Monitoring System For Firefighters And Visually Impaired, Siddhesh R. Gandhi

Masters Theses 1911 - February 2014

ABSTRACT

A REAL TIME INDOOR NAVIGATION AND MONITORING SYSTEM FOR FIREFIGHTERS AND VISUALLY IMPAIRED

MAY 2011

SIDDHESH RAJAN GANDHI

M.S. E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERST

Directed by: Professor Aura Ganz

There has been a widespread growth of technology in almost every facet of day to day life. But there are still important application areas in which technology advancements have not been implemented in a cost effective and user friendly manner. Such applications which we will address in this proposal include: 1) indoor localization and navigation of firefighters during rescue operations and 2) indoor localization and navigation for the blind and …

Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj

Masters Theses 1911 - February 2014

Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance …

Application Specific Customization And Scalability Of Soft Multiprocessors, Deepak C. Unnikrishnan

Masters Theses 1911 - February 2014

Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After …

Implementation Of Data Path Credentials For High-Performance Capabilities-Based Networks, Kamlesh T. Vasudevan

Masters Theses 1911 - February 2014

Capabilities-based networks present a fundamental shift in the security design of network architectures. Instead of permitting the transmission of packets from any source to any destination, routers deny forwarding by default. For a successful transmission, packets need to positively identify themselves and their permissions to the router. A major challenge for a high performance implementation of such a network is an efficient design of the credentials that are carried in the packet and the verification procedure on the router. A network protocol that implements data path credentials based on Bloom filters is presented in this thesis. Our prototype implementation shows …

A Hardware Framework For Yield And Reliability Enhancement In Chip Multiprocessors, Abhisek Pan

Masters Theses 1911 - February 2014

Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. Today an increasing number of hardware failures are attributed to device reliability problems that cause partial system failure or shutdown. Also maintaining an acceptable manufacturing yield is seen as challenge because of smaller feature sizes, process variation, and reduced headroom for burn-in tests. In this project we investigate a hardware-based scheme for improving yield and reliability of a homogeneous chip multiprocessor (CMP). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multi-core system to keep the system operational in …