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Reliability Modeling And Analysis Of Clockless Wave Pipeline Core For Embedded Combinational Logic Design, Tao Feng, Noh-Jin Park, Minsu Choi, Nohpill Park

Electrical and Computer Engineering Faculty Research & Creative Works

This paper presents a model for analyzing the reliability of a clockless wave pipeline as an intellectual property (IP) core for embedded design. This design requires different clocking requirements by each embedded IP core during integration. Therefore, either partial or global lack of synchronization of the embedded clocking is considered for the data flow. The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous IP logic cores embedded in system-on-chip (SoC). A clockless wave pipeline technique relies on local asynchronous operation for seamless …