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Full-Text Articles in Engineering
Oscillation Built-In-Self-Test For Adc Linearity Testing In Deep Submicron Cmos Technology, Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong, Adam Osseiran
Oscillation Built-In-Self-Test For Adc Linearity Testing In Deep Submicron Cmos Technology, Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong, Adam Osseiran
Research outputs 2013
This paper proposes an Oscillation BIST (OBIST) that is meant to test ADCs fabricated in sub 100nm processes. The design is intended to be capable of testing a 10-bit ADC that was designed in 40nm CMOS. The design scheme presents a simple analog stimulus generator that was designed in 40nm CMOS together with schematic based simulation results. There is also a description of a calibration circuit and a highlevel implementation of a BIST control system to run the BIST and to calculate static parameters such as Differential Non-linearity (DNL) and Integral Non-linearity (INL). Simulation results for the analog stimulus generator …
Effect Of A Polywell Geometry On A Cmos Photodiode Array, Paul V. Jansz, Steven Hinckley, Graham Wild
Effect Of A Polywell Geometry On A Cmos Photodiode Array, Paul V. Jansz, Steven Hinckley, Graham Wild
Research outputs pre 2011
The effect of a polywell geometry hybridized with a stacked gradient poly-homojunction architecture, on the response of a CMOs compatible photodiode array was simulated. Crosstalk and sensitivity improved compared to the polywell geometry alone, for both back and front illumination
Simulation Of A Hybrid Polywell And Stacked Gradient Poly-Homojunction Cmos Photodiode, Paul V. Jansz, Steven Hinckley
Simulation Of A Hybrid Polywell And Stacked Gradient Poly-Homojunction Cmos Photodiode, Paul V. Jansz, Steven Hinckley
Research outputs pre 2011
In this paper, we have simulated the performance of a photodiode array that has multiple wells per pixel as well as a stacked-gradient poly-homojunction (StaG) geometry. The pixel response resolution was improved when the first StaG epilayer was within 2 μm of the space charge region (SCR).