Engineering Commons^™

Quickbooks Self-Employed Ios Application, Braden Young

Computer Science and Software Engineering

No abstract provided.

Team Omnimouse, Derek J. Halman, Josh B. Porter, Steven A. Silver, Ian S. Stemper

Computer Engineering

INFORMATION, DATA, FIGURES AND DRAWINGS EMBODIED IN THIS DOCUMENT ARE STRICTLY CONFIDENTIAL AND ARE SUPPLIED ON THE UNDERSTANDING THAT THEY WILL NOT BE DISCLOSED TO THIRD PARTIES WITHOUT THE PRIOR WRITTEN CONSENT OF QUALITY OF LIFE PLUS.

Chromium Os On Freescale I.Mx6q, Pushpal Sidhu

Computer Engineering

This projects intention is to get Chromium OS running on a Freescale i.MX6q processor, a processor based on the ARM® Cortex™-A9 architecture. The development board I used is the Ventana GW5400 by Gateworks. This project inherently meant using Chromium OS's development system which meant I created a board specific package for the Ventana single board computer. This project is a proof of concept that can mean extending Chromium OS to various implementations of the ARM® Cortex™-A9 architecture.

Implementing A Robust Data Storage Software System For Cp9, Stuart Andrew Weickgenant

Computer Engineering

This project focuses on the continuation of the CP9 CubeSat project, specifically the software which will be running on the satellite when it goes into space. This project mostly goes into designing a robust system which stores the data collected from the sensors on board CP9, whose purpose is to collect vibrations data from its launch vehicle during its ascent into space, into an easy to analyze system once the data is downlinked to PolySat’s ground station after launch. One other thing this system does is to prevent CP9 from collecting unnecessary data after launch. Testing was done on this …

Design Of Cpu Simulation Software For Armv7 Instruction Set Architecture, Dillon Tellier

Computer Engineering

Simulations have long been a part of the engineering process in both the professional and academic domain. From a pedagogic standpoint, simulations allow students to explore the dynamics of engineering scenarios by controlling variables, taking measurements, and observing behavior which would be difficult or impossible without simulation. One such tool is a CPU simulator used in Cal Poly’s Computer Architecture classes; this software simulates an instruction accurate operation of a computer processor and reports statistics regarding the execution of the supplied compiled machine code. For the last several years Cal Poly’s computer architecture classes have used a previous version of …

Designing A Modular Dsp Core For Real-Time Audio Performance, Kevin Richard Brewer

Computer Engineering

This project provides an overview for building a Digital Signal Processing (DSP) core on a Digilent Nexys2 FPGA board. The DSP core is designed to give Cal Poly students interested in DSP and its applications to audio engineering a usable platform to perform signal processing and analytics. The processes of the DSP core are modular, allowing students to design their own implementations of various adder and multiplier functions. Infinite impulse response (IIR) filters and finite impulse response (FIR) filters using both cascade and parallel implementations are the primary processing tools in the core, and all output can be visually and …

Ecs Game Engine Design, Daniel Masamune Hall

Computer Engineering

Game programming design and organization can be difficult and complicated. To simplify the development process, frameworks with an array of tools and utilities known as game engines are used. The main goal of this project is to explore game engine designs and develop a design for a modular and expandable game engine. The designs covered in this paper are Object Oriented Programing (OOP) and two Entity Component System (ECS). OOP designs, commonly used in computer science, use a hierarchy of objects to share functionality. ECS designs are based off of the concepts Composition over inheritance in which objects contain features …

Regen: Optimizing Genetic Selection Algorithms For Heterogeneous Computing, Scott Kenneth Swinkleb Winkleblack

Master's Theses

GenSel is a genetic selection analysis tool used to determine which genetic markers are informational for a given trait. Performing genetic selection related analyses is a time consuming and computationally expensive task. Due to an expected increase in the number of genotyped individuals, analysis times will increase dramatically. Therefore, optimization efforts must be made to keep analysis times reasonable.

This thesis focuses on optimizing one of GenSel’s underlying algorithms for heterogeneous computing. The resulting algorithm exposes task-level parallelism and data-level parallelism present but inaccessible in the original algorithm. The heterogeneous computing solution, ReGen, outperforms the optimized CPU implementation achieving a …

Decafs: A Modular Distributed File System To Facilitate Distributed Systems Education, Halli Elaine Meth

Master's Theses

Data quantity, speed requirements, reliability constraints, and other factors encourage industry developers to build distributed systems and use distributed services. Software engineers are therefore exposed to distributed systems and services daily in the workplace. However, distributed computing is hard to teach in Computer Science courses due to the complexity distribution brings to all problem spaces. This presents a gap in education where students may not fully understand the challenges introduced with distributed systems. Teaching students distributed concepts would help better prepare them for industry development work.

DecaFS, Distributed Educational Component Adaptable File System, is a modular distributed file system designed …

Virtual Reality Engine Development, Varun Varahamurthy

Master's Theses

With the advent of modern graphics and computing hardware and cheaper sensor and display technologies, virtual reality is becoming increasingly popular in the fields of gaming, therapy, training and visualization. Earlier attempts at popularizing VR technology were plagued by issues of cost, portability and marketability to the general public. Modern screen technologies make it possible to produce cheap, light head-mounted displays (HMDs) like the Oculus Rift, and modern GPUs make it possible to create and deliver a seamless real-time 3D experience to the user. 3D sensing has found an application in virtual and augmented reality as well, allowing for a …

Optimizing Lempel-Ziv Factorization For The Gpu Architecture, Bryan Ching

Master's Theses

Lossless data compression is used to reduce storage requirements, allowing for the relief of I/O channels and better utilization of bandwidth. The Lempel-Ziv lossless compression algorithms form the basis for many of the most commonly used compression schemes. General purpose computing on graphic processing units (GPGPUs) allows us to take advantage of the massively parallel nature of GPUs for computations other that their original purpose of rendering graphics. Our work targets the use of GPUs for general lossless data compression. Specifically, we developed and ported an algorithm that constructs the Lempel-Ziv factorization directly on the GPU. Our implementation bypasses the …

Twill: A Hybrid Microcontroller-Fpga Framework For Parallelizing Single- Threaded C Programs, Douglas S. Gallatin

Master's Theses

Increasingly System-On-A-Chip platforms which incorporate both micropro- cessors and re-programmable logic are being utilized across several fields ranging from the automotive industry to network infrastructure. Unfortunately, the de- velopment tools accompanying these products leave much to be desired, requiring knowledge of both traditional embedded systems languages like C and hardware description languages like Verilog. We propose to bridge this gap with Twill, a truly automatic hybrid compiler that can take advantage of the parallelism inherent in these platforms. Twill can extract long-running threads from single threaded C code and distribute these threads across the hardware and software domains to more …

Compacting Loads And Stores For Code Size Reduction, Isaac Asay

Master's Theses

It is important for compilers to generate executable code that is as small as possible, particularly when generating code for embedded systems. One method of reducing code size is to use instruction set architectures (ISAs) that support combining multiple operations into single operations. The ARM ISA allows for combining multiple memory operations to contiguous memory addresses into a single operation. The LLVM compiler contains a specific memory optimization to perform this combining of memory operations, called ARMLoadStoreOpt. This optimization, however, relies on another optimization (ARMPreAllocLoadStoreOpt) to move eligible memory operations into proximity in order to perform properly. This mover optimization …