Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 3 of 3
Full-Text Articles in Engineering
A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus
A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus
Theses and Dissertations
This study explores the idea of building a library of VHDL configurable components for use in digital radar applications. Configurable components allows a designer to choose which components he or she needs and configures those components for a specific application. By doing this, design time for ASICs and FPGAs is shortened because the components are already designed and tested. This idea is demonstrated with a configurable dynamic pipelinable fast fourier transform. Many FFT implementations exist, but this implementation is both configurable and dynamic. Pre-synthesis customization allows the FFT to be tailored to almost any DSP application, and the dynamic property …
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Theses and Dissertations
This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …