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Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Theses and Dissertations
This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.