Engineering Commons^™

A C To Register Transfer Level Algorithm Using Structured Circuit Templates: A Case Study With Simulated Annealing, Jonathan D. Phillips

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

A tool flow is presented for deriving simulated annealing accelerator circuits on a field programmable gate array (FPGA) from C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based Autonomous Mission Planning and Scheduling (AMPS) software used for autonomous spacecraft systems is explained. The goal of the research is an automated method for the derivation of a hardware design that maximizes performance while minimizing the FPGA footprint. Results obtained are compared with a peer C to register transfer level (RTL) logic tool, a state-of-the-art …