Engineering Commons^™

Assuring Netlist-To-Bitstream Equivalence Using Physical Netlist Generation And Structural Comparison, Reilly Mckendrick, Jeffrey Goeders, Keenan Faulkner

Faculty Publications

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendor-provided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design’s conversion to bitstream. However, motivated attackers may alter the CAD tools’ integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation …

Leveraging Fpga Primitives To Improve Word Reconstruction During Netlist Reverse Engineering, Reilly Mckendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders

Faculty Publications

While attempting to perform hardware trojan detection, or other low-level design analyses, it is often necessary to inspect and understand the gate-level netlist of an implemented hardware design. Unfortunately this process is challenging, as at the physical level, the design does not contain any hierarchy, net names, or word groupings. Previous work has shown how gate-level netlists can be analyzed to restore high-level circuit structures, including reconstructing multi-bit signals, which aids a user in understanding the behavior of the design. In this work we explore improvements to the word reconstruction process, specific to FPGA platforms. We demonstrate how hard-block primitives …

Design Of Hardware To Aid Smartphone-Based Oscilloscope App, Riddock Moran

Honors Theses

A smartphone-based oscilloscope improves on traditional lab oscilloscopes in accessibility and portability but faces several performance limitations compared to traditional oscilloscopes. Among these, an oscilloscope app that uses the phone’s audio to read voltage signals will have a sampling rate and voltage bottlenecked by the capabilities of the audio codec, which will rarely exceed a rate of 48 kHz and 1 volt, respectively. Additionally, smartphones lack the ability to read line-in audio, allowing only one channel input through the microphone. Direct connections to an audio source may not be possible due to requiring an audio jack connection, and different poles …

Structural Checking Tool Restructure And Matching Improvements, Derek Taylor

Graduate Theses and Dissertations

With the rising complexity and size of hardware designs, saving development time and cost by employing third-party intellectual property (IP) into various first-party designs has become a necessity. However, using third-party IPs introduces the risk of adding malicious behavior to the design, including hardware Trojans. Different from software Trojan detection, the detection of hardware Trojans in an efficient and cost-effective manner is an ongoing area of study and has significant complexities depending on the development stage where Trojan detection is leveraged. Therefore, this thesis research proposes improvements to various components of the soft IP analysis methodology utilized by the Structural …

A Precise Dispenser Design For Canine Cognition Research, Walker Arce, Jeffrey R. Stevens

Department of Electrical and Computer Engineering: Faculty Publications

Some forms of canine cognition research require a dispenser that can accurately dispense precise quantities of treats. When using off-the-shelf or retrofitted dispensers, there is no guarantee that a precise number of treats will be dispensed. Often, they will over-dispense treats, which may not be acceptable for some tasks. Here we describe a 3D-printed precise treat dispenser with a 59-treat capacity driven by a stepper motor drive and controlled by an integrated Raspberry Pi. The dispenser can be built for less than 200 USD and is fully 3D printable. While off-the-shelf dispensers can result in an error rate of 20–30%, …

Cellular Service With Settlement-Free Peering, Shahzeb Mustafa, Sayanta Seth, Murat Yuksel, Mostafizur Rahman

Electrical and Computer Engineering Faculty Publications and Presentations

Despite several iconic innovations in wireless networks, cellular service still remains largely unreliable with regards to non-urban network coverage. Cellular providers often need to make roaming agreements among each other for serving their customers with basic connectivity in areas where they do not have coverage. Considering all the technical limitations of domestic roaming, we present a “wireless peering” model for settlement-free spectrum sharing. It allows providers to extend their coverage to “off-network” regions without any hardware modifications. Its software-defined nature makes the model highly scalable, easy to deploy and cost-effective. Simulation results show a significant improvement in off-network wireless speed, …

Portable Ventilator, Bradley C. Weeks, Jack W. Brewer, Sanders Sanabria

Electrical Engineering

The current COVID-19 pandemic has heavily impacted the healthcare system in the United States and elsewhere. The need for patients to have access to a hospital with a ventilator along with a shortage of ventilators for recovery and at-home care as a result of minimal hospital vacancy for patients has been greatly stressed. The presented problem is both an unmet demand and supply of portable and effective ventilators. Existing ventilators have many shortcomings that should be addressed: size, weight, cost, and complexity of current ventilators confines users to stay in a medical facility whilst being monitored by professionals. This both …

Hardware Implementations Of Ccsds Deep Space Ldpc Codes For A Satellite Transponder, Dana R. Sorensen

All Graduate Plan B and other Reports, Spring 1920 to Spring 2023

Error-correction coding is a technique that adds mathematical structure to a message, allowing corruptions to be detected and corrected when the message is received. This is especially important for deep space satellite communications, since the long distances and low signal power levels often cause message corruption. A very strong type of error-correction coding known as LDPC codes was recently standardized for use with space communications. This project implements the encoding and decoding algorithms required for a small satellite radio to be able to use these LDPC codes. Several decoder architectures are implemented and compared by their performance, speed, and complexity. …

An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke

Graduate Theses and Dissertations

The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …

Hybrid Rocket Engine Ignition And Control, Benjamin Letourneau, Trevor Blampied, Megan Johnson, Thomas Pham

Honors Theses and Capstones

Control of a hybrid rocket engine is dependent upon a robust system capable of executing commands at precise times. In order to accomplish this, hardware systems must be in place to control the flow of a pressurized gas and provide feedback to launch site personnel. Through the use of solenoid valves and wireless transceivers, control over the thrust of a rocket can be accomplished. In order to understand this information and provide a user-friendly interface to complete this, a launch control module is used. Through the combined capabilities of the two system it becomes possible to test and launch a …

Statistical Analysis Of A Channel Emulator For Noisy Gradient Descent Low Density Parity Check Decoder, Rakin Muhammad Shadab

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into …

Hardware Ip Classification Through Weighted Characteristics, Brendan Mcgeehan

Graduate Theses and Dissertations

Today’s business model for hardware designs frequently incorporates third-party Intellectual Property (IP) due to the many benefits it can bring to a company. For instance, outsourcing certain components of an overall design can reduce time-to-market by allowing each party to specialize and perfect a specific part of the overall design. However, allowing third-party involvement also increases the possibility of malicious attacks, such as hardware Trojan insertion. Trojan insertion is a particularly dangerous security threat because testing the functionality of an IP can often leave the Trojan undetected. Therefore, this thesis work provides an improvement on a Trojan detection method known …

Automated Compilation Test System For Embedded System, Mohamad Khairi Ishak, Ooi Jun Hwan, Teh Jiashen, Nor Ashidi Mat Isa

Makara Journal of Technology

Embedded system testing involves testing an integration of software and hardware. It is increasingly difficult to evaluate the functionality of each module within a short time because of the increasing number of tests required. In this paper, a novel stepwise methodology involving the use of an automated compilation test system (ACTS) is proposed, to improve the quality of testing and optimize the testing time using automation. Using the proposed method, the testing coverage can be maximized, while minimizing the manual work and testing time required. This ACTS was used to automate the test code compilation and execution for different hardware …

Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally

Information Science Faculty Publications

One of the most important Internet of Things applications is the wireless body sensor network (WBSN), which can provide universal health care, disease prevention, and control. Due to large deployments of small scale smart sensors in WBSNs, security, and privacy guarantees (e.g., security and safety-critical data, sensitive private information) are becoming a challenging issue because these sensor nodes communicate using an open channel, i.e., Internet. We implement data integrity (to resist against malicious tampering) using the secure hash algorithm 3 (SHA-3) when smart sensors in WBSNs communicate with each other using the Internet. Due to the limited resources (i.e., storage, …

Design, Simulation, And Hardware Construction Of A 600 W Solid State Dc Circuit Breaker For The Dc House Project, Calin Matthew Bukur

Master's Theses

DC circuit breakers must be able to arrest overcurrent conditions to prevent electrical equipment and wiring from causing building fires or other hazards from occurring. With more DC renewable sourced structures such as Cal Poly’s DC House, an inexpensive and reliable protection system is necessary to ensure safe energy transfer to the loads. One method of protecting a system is preventing excessive amounts of current to be drawn by the load when the surrounding components are rated at a lesser value. DC circuit breakers act as a monitoring system and barely presents an effect on the voltage or power. With …

Oracle Guided Incremental Sat Solving To Reverse Engineer Camouflaged Circuits, Xiangyu Zhang

Masters Theses

This study comprises two tasks. The first is to implement gate-level circuit camouflage techniques. The second is to implement the Oracle-guided incremental de-camouflage algorithm and apply it to the camouflaged designs.

The circuit camouflage algorithms are implemented in Python, and the Oracle- guided incremental de-camouflage algorithm is implemented in C++. During this study, I evaluate the Oracle-guided de-camouflage tool (Solver, in short) performance by de-obfuscating the ISCAS-85 combinational benchmarks, which are camouflaged by the camouflage algorithms. The results show that Solver is able to efficiently de-obfuscate the ISCAS-85 benchmarks regardless of camouflaging style, and is able to do so 10.5x …

Solid State Drive, Shaun A. Steele

Electrical Engineering

This project documents the design and implementation of a solid state drive (SSD). SSDs are a non-volatile memory storage device that competes with hard disk drives. SSDs rely on flash memory, a type of non-volatile memory that is electrically erased and programmed. The appeal of SSDs lies in the fact that they allow a fast, reliable, and durable memory storage device. The goal of this project is to have a working external SSD built from scratch.

Hardware Design Theory (Using Raspberry Pi), Anthony Kelly, Thomas Blum Dr.

Undergraduate Research

The concept for this research proposal is focused on achieving three main objectives:

1) To understand the logic and design behind the Raspberry Pi (RbP) mini-computer model, including: all hardware components and their functions, the capabilities [and limits] of the RbP, and the circuit engineering for these components.

2) To be able to, using the Python high-level language, duplicate, manipulate, and create RbP projects ranging from basic user-input and response systems to the theories behind more intricate and complicated observatory sensors.

3) Simultaneously, in order to combine a mutual shared interest of History and to blend in work done within …

High-Speed Programmable Fpga Configuration Memory Access Using Jtag, Ammon Bradley Gruwell

Theses and Dissertations

Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration …

Development Of Microgrid Test Bed For Testing Energy Management System, Shaili Nepal

Electronic Theses and Dissertations

Today the world population has reached 7.5 billion, and this number is expected to grow at the rate of 1.13% every year [1]. With this increase in population, the total demand for electricity has also increased. More people means the need for more power: electricity to power homes, schools, industries, hospitals, and so on. In today’s world, where most of the daily activities are dependent on electricity, demand for electricity, therefore, continues to rise. Currently, managing this growing need for electricity is one of the challenges the world is facing. In addition to this, approximately 1.2 billion people live in …

Scaled Synthetic Aperture Rader Development, Jason Garvey Schray

Master's Theses

Several previous Cal Poly thesis projects involve synthetic aperture radar (SAR), automatic target recognition (ATR), and tracking. SAR data was either accessed from a publicly available database or generated using complex computer modeling software. The motivation for this dual thesis project is to design and construct a scaled SAR system to support Cal Poly radar projects. Ideally this is a low-cost, high resolution SAR architecture that produces raw range Doppler data for any desired target area. To that end, a scaled SAR system was successfully designed, built, and tested. The current SAR system, however, does not perform azimuthal compression and …

A Hardware Based Audio Event Detection System, Jacob Daniel Tobin

Masters Theses

Audio event detection and analysis is an important tool in many fields, from entertainment to security. Recognition technologies are used daily for parsing voice commands, tagging songs, and real time detection of crimes or other undesirable events. The system described in this work is a hardware based application of an audio detection system, implemented on an FPGA. It allows for the detection and characterization of gunshots and other events, such as breaking glass, by comparing a recorded audio sample to 20+ stored fingerprints in real time. Additionally, it has the ability to record flagged events and supports integration with mesh …

Asynchronous Advanced Encryption Standard Hardware With Random Noise Injection For Improved Side-Channel Attack Resistance, Siva Pavan Kumar Kotipalli, Yong-Bin Kim, Minsu Choi

Electrical and Computer Engineering Faculty Research & Creative Works

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly …

Real-Time Color Treebasis Feature Matching On A Limited-Resource Hardware System, Garrett Sean Hartman

Theses and Dissertations

This research has been conducted in order to create a robust, lightweight feature detecting and matching algorithm that builds upon the foundation set by the TreeBASIS algorithm. The goal is to create a color-based version of the TreeBASIS algorithm that uses less hardware resources than the original, is more accurate in its matching capabilities, can successfully be deployed on a resource-limited FPGA platform, and can process in real time. This thesis first presents the newly designed hardware tri-channel FAST Feature Detector that finds features in color. Next the TreeBASIS algorithm is analyzed to discover what improvements can be made in …

Protecting Network Processors With High Performance Logic Based Monitors, Harikrishnan Kumarapillai Chandrikakutty

Masters Theses 1911 - February 2014

Technological advancements have transformed the way people interact with the world. The Internet now forms a critical infrastructure that links different aspects of our life like personal communication, business transactions, social networking, and advertising. In order to cater to this ever increasing communication overhead there has been a fundamental shift in the network infrastructure. Modern network routers often employ software programmable network processors instead of ASIC-based technology for higher throughput performance and adaptability to changing resource requirements. This programmability makes networking infrastructure vulnerable to new class of network attacks by compromising the software on network processors. This issue has resulted …

Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman

Masters Theses 1911 - February 2014

Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much faster and much more robust protocol than its predecessor, ATA (also referred to as Parallel ATA or IDE). Many hardware designs, including those using Field-Programmable Gate Arrays (FPGAs), have a need for a long-term storage solution, and a hard drive would be ideal. One such design is the high-speed Data Acquisition System (DAS) created for the NASA Surface Water and Ocean Topography mission. This system utilizes a Xilinx Virtex-4 FPGA. Although the DAS includes a SATA …

Synthesis Of Multiple-Input Translinear Element Networks, Bradley Minch, Paul Hasler, Chris Diorio

Bradley Minch

We describe two systematic procedures for synthesizing multiple-input translinear element (MITE) networks that produce an output current that is equal to product of a number of input currents, each of which is raised to an arbitrary rational power. By using the first procedure, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. By using the second procedure, we arrive at a MITE network, called a cascade network, that reduces the fan-in required of each MITE. We illustrate each ofthese procedures with an example.

Investigation Of The Divcon Neuron To Increase The Performance Of A Traditional Feed Forward Multi-Layer Perceptron And Its Hardware Implementation, Jovan Saenz

Open Access Theses & Dissertations

ABSTRACT

Artificial Neural Networks (ANNs) have been developed in an attempt to emulate the information processing capabilities of the biological brain. They offer an alternate computing approach to problems in which mathematical modeling is complicated, such as pattern recognition and pattern classification.

Since ANNs were proposed in the early 1940s, there has been a great amount of research effort dedicated to the development of new models that improve performance. Consequently, different architectures, a variety of activation functions, and distinct learning algorithms have been developed and implemented in different disciplines such as medicine, engineering, and science. In addition, ANNs have been …

Blue-Box Approach To Power Electronics And Machines Educational Laboratories, Robert S. Balog, Zakdy Sorchini, Jonathan W. Kimball, Patrick L. Chapman, Philip T. Krein, Peter W. Sauer

Electrical and Computer Engineering Faculty Research & Creative Works

Our approach to laboratory education in power electronics and electric machines is presented. The approach centers upon "blue-box" laboratory components, that aid the student in rapid experiment assembly without disguising important aspects of the hardware. Several example experiments are presented. Schematics and construction techniques for the hardware are publicly available.