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Full-Text Articles in Engineering
Speeding Up Vlsi Layout Verification Using Fuzzy Attributed Graphs Approach, Nian Zhang, Donald C. Wunsch
Speeding Up Vlsi Layout Verification Using Fuzzy Attributed Graphs Approach, Nian Zhang, Donald C. Wunsch
Electrical and Computer Engineering Faculty Research & Creative Works
Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intel's 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm2 chip size with …
The Subcircuit Extraction Problem, Nian Zhang, Donald C. Wunsch, Frank Harary
The Subcircuit Extraction Problem, Nian Zhang, Donald C. Wunsch, Frank Harary
Electrical and Computer Engineering Faculty Research & Creative Works
The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of …
Extracting Cad Models For Quantifying Noise Coupling Between Vias In Pcb Layouts, Shaofeng Luan, Jun Fan, W. Liu, Fengchao Xiao, James L. Knighten, Norman W. Smith, Ray Alexander, Jim Nadolny, Yoshio Kami, James L. Drewniak
Extracting Cad Models For Quantifying Noise Coupling Between Vias In Pcb Layouts, Shaofeng Luan, Jun Fan, W. Liu, Fengchao Xiao, James L. Knighten, Norman W. Smith, Ray Alexander, Jim Nadolny, Yoshio Kami, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are …
An Algorithm For Automated Printed Circuit Board Layout And Routing Evaluation, Todd H. Hubing, Thomas Van Doren, James L. Drewniak, Puneet Grover, R. Lee Hill
An Algorithm For Automated Printed Circuit Board Layout And Routing Evaluation, Todd H. Hubing, Thomas Van Doren, James L. Drewniak, Puneet Grover, R. Lee Hill
Electrical and Computer Engineering Faculty Research & Creative Works
An algorithm has been developed to evaluate printed circuit boards that are designed using automated board layout and routing software. The algorithm analyzes aspects of component placement and trace routing while searching for violations of basic EMC design principles. The algorithm is implemented in code designed to work with a widely used board layout and routing program. This code can help novice and experienced circuit board designers to avoid mistakes that may result in serious electromagnetic compatibility problems.