Engineering Commons^™

Nanosecond Peak Detect And Hold Circuit With Adjustable Dynamic Range, Gabriel Fellner, Lucas Speckbacher, Seyed Mostafa Mousavi, David Johannes Pommerenke, Satyajeet Shinde, Michael Hillstrom, Ram Chundru, Cheung Wei Lam

Electrical and Computer Engineering Faculty Research & Creative Works

This article presents a novel peak detect and hold (PDH) circuit for the measurement of the peak voltage of electromagnetic-field probes. These probes are used to capture the fields generated by electrostatic discharge (ESD) events in nongrounded portable devices. Therefore, a circuit combining small size, low power consumption, and nanosecond operation is needed. A topology using a discrete bipolar transistor structure with operational transconductance amplifier (OTA) and common-base storage capacitor charge control optimally meets the requirements. The circuit performance is demonstrated for different bias point settings. The error between the captured value and the actual pulse peak value is shown …

Low Power Multi-Channel Interface For Charge Based Tactile Sensors, Samuel Hansen

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

Analog front end electronics are designed in 65 nm CMOS technology to process charge pulses arriving from a tactile sensor array. This is accomplished through the use of charge sensitive amplifiers and discrete time filters with tunable clock signals located in each of the analog front ends. Sensors were emulated using Gaussian pulses during simulation. The digital side of the system uses SAR (successive approximation register) ADCs for sampling of the processed sensor signals.

Adviser: Sina Balkır

Electronically Tunable Grounded/Floating Inductance Simulators Using Z-Copy Cfccc, Alok Kumar Singh, Pragati Kumar, Raj Senani

Turkish Journal of Electrical Engineering and Computer Sciences

In this paper, new electronically tunable grounded and floating inductance simulators employing a Z-copy current follower current controlled conveyor (CFCCC) and one grounded capacitor have been proposed and their workability has been demonstrated by PSPICE simulations in 0.18-$\mu $m TSMC CMOS technology.

Accelerating The Solving Of Nonlinear Equations Using The Homotopy Method: Application On Finding The Operating Point Of Complex Circuits, Fathi Dhiabi, Mohamed Boumehraz

Turkish Journal of Electrical Engineering and Computer Sciences

Analog circuits with nonlinear elements (e.g., diode, BJT, and CMOS) and integrated circuits are very complex systems. As a result, they are very difficult to analyze because of the need to generate a nonlinear equation system solution in order to do so. Solving nonlinear equations is still a challenging problem. Iterative methods, however, are frequently used to solve them. This paper describes a method that can be used to both accelerate the solving of nonlinear equations and find the operating point in various integrated circuits by construction of the global homotopy equation of the analog circuit. This is done by …

Synthesis Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch

Bradley Minch

In this paper, we present a methodology for synthesizing analog systems using a class of circuits called dynamic translinear circuits. We illustrate this method by synthesizing part of a Least-Mean-Squares (LMS) adaptation algorithm used in an analog adaptive filter. We present preliminary experimental results from a chip fabricated ina 0.5-μm double-poly CMOS process.

A Long-Channel Model For The Asymmetric Double-Gate Mosfet Valid In All Regions Of Operation, Abhishek Kammula, Bradley Minch

Bradley Minch

We present a physically based, continuous analytical model for long-channel double-gate MOSFETs. The model is particularly well suited for implementation in circuit simulators due to the simple expressions for the current andthe continuous nature of the derivatives of the current which improves convergence behavior.

Low Voltage And Performance Tunable Cmos Circuit Design Using Independently Driven Double Gate Mosfets, Arvind Kumar, Bradley Minch, Sandip Tiwari

Bradley Minch

Independently driven double-gate MOSFETs (DGFETs) facilitate design of analog circuits under digital logic constraints and provide in-circuit parameter adaptability through threshold voltage control. Threshold voltagetuning is achieved by biasing one of the two gates where as strong coupling of surface potentials at the two interfaces provides a low resistance feedback path. The geometry also allows a back-floating gate NVRAM structure with superior scalability and floating gate related analog applications without any read disturbance. This paper gives examples across breadth of circuits where this tunability is exploited.

Floating-Gate Techniques For Assessing Mismatch, Bradley Minch

Bradley Minch

I discuss the importance of capacitor matching in the context of using charge stored on floating-gate MOS (FGMOS) transistors to compensate for transistor mismatch in analog circuits. I describe a simple technique that only involves static measurements for assessing the relative mismatch between capacitors. I also show experimental measurements of capacitor mismatch for small capacitors fabricated in 1.2-μm and 0.35-μm double-poly it n-well CMOS process that are commonly available.

Fault Coverage Measurement Technique For Analog Circuits, E. Paul Ratazzi

Electrical Engineering and Computer Science - All Scholarship

This report describes an effort to develop a technique for measuring the amount of fault detection coverage that an analog test pattern has for a particular analog device. The technique is based on a software tool which statistically analyzes data from a circuit simulator. One example of a fault simulation experiment is presented, and some of the results are discussed. Finally, some ideas for future work in this area are given.