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Full-Text Articles in Engineering
Synthesis Of High-Temperature Stable Anatase Tio2 Photocatalyst, Suresh Pillai, Declan Mccormack, Michael Seery, Pradeepan Periyat, Steven Hinder, John Colreavy, Reenamol George, Hugh Hayden
Synthesis Of High-Temperature Stable Anatase Tio2 Photocatalyst, Suresh Pillai, Declan Mccormack, Michael Seery, Pradeepan Periyat, Steven Hinder, John Colreavy, Reenamol George, Hugh Hayden
Articles
In the absence of a dopant or precursor odification, anatase to rutile transformation in synthetic TiO2 sually ccurs at a temperature of 600 700 °C. Conventionally, metal oxide dopants (e.g., Al2O3 nd SiO2 are used o tune the anatase to rutile transformation. A simple methodology is reported here to extend the anatase utile transformation by employing various concentrations of urea. XRD and Raman spectroscopy were used uring thermal treatment. A significantly higher anatase phase (97%) as been obtained at 800 C with use of a 1:1 Ti(OPr)4 urea composition and 11% anatase composition is etained even after calcining …
Reducing Energy In Fpga Multipliers Through Glitch Reduction - Clock Power And Digit-Serial Addendum, Nathaniel Rollins, Michael J. Wirthlin
Reducing Energy In Fpga Multipliers Through Glitch Reduction - Clock Power And Digit-Serial Addendum, Nathaniel Rollins, Michael J. Wirthlin
Faculty Publications
Sponsorship: NASA. In a previous paper it was shown that reducing the amount of glitches in digital designs can significantly reduce the amount of dynamic power consumption. Pipelined multipliers and a bit-serial multiplier design were used to show this. The paper failed to mention how much of the dynamic power consumption was due to the clock distribution. Also the only digit- serial multiplier digit size investigated was a digit size of 1. This paper addresses the issue of dynamic clocking power and includes results of digit-serial multipliers with larger digit sizes.