Open Access. Powered by Scholars. Published by Universities.®
- Keyword
-
- Iddq (2)
- 16-bit images (1)
- ADC (1)
- Acquistion (1)
- Adc (1)
-
- Architecture (1)
- Buildgates (1)
- Built-in current sensor (1)
- Cadence (1)
- Camera (1)
- Cameralink (1)
- Computer architecture (1)
- Critical subtree (1)
- D-sequences (1)
- DWT (1)
- Design (1)
- Digital watermarking (1)
- Dynamically scheduled (1)
- Embedded (1)
- Fast data transfer (1)
- Fetch unit (1)
- Fill unit (1)
- Floating gate MOSFETs (1)
- Framegrabber (1)
- High frame rate (1)
- Ide (1)
- Images (1)
- Linear generator (1)
- Modelsim (1)
- Modulator (1)
Articles 1 - 8 of 8
Full-Text Articles in Engineering
Design And Performance Of Electric Shock Absorber, Oly D. Paz
Design And Performance Of Electric Shock Absorber, Oly D. Paz
LSU Master's Theses
The electric shock absorber is a device that converts the kinetic energy of an oscillating object into electric energy. This kinetic energy is normally dumped in a form of thermal energy in a conventional, mechanical shock absorber. The electric shock absorber consists of a permanent magnet linear synchronous generator (PMLSG), a spring, and an electric energy accumulator. The major goal of the project is to design and analyze the operation of an electric shock absorber. In order to define the initial requirements that the electric shock absorber has to satisfy, the construction and performance of currently used shock absorbers were …
Testing A Cmos Operational Amplifier Circuit Using A Combination Of Oscillation And Iddq Test Methods, Pavan K. Alli
Testing A Cmos Operational Amplifier Circuit Using A Combination Of Oscillation And Iddq Test Methods, Pavan K. Alli
LSU Master's Theses
This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability …
Iddq Testing Of A Cmos First Order Sigma-Delta Modulator Of An 8-Bit Oversampling Adc, Anand K. Chamakura
Iddq Testing Of A Cmos First Order Sigma-Delta Modulator Of An 8-Bit Oversampling Adc, Anand K. Chamakura
LSU Master's Theses
This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on …
Zooplankton Visualization System: Design And Real-Time Lossless Image Compression, Dattatreya Reddy Tetala Satya Surya
Zooplankton Visualization System: Design And Real-Time Lossless Image Compression, Dattatreya Reddy Tetala Satya Surya
LSU Master's Theses
In this thesis, I present a design of a small, self-contained, underwater plankton imaging system. I base the imaging system’s design on an embedded PC architecture based on PC/104-Plus standards to meet the compact size and low power requirements. I developed a simple graphical user interface to run on a real-time operating system to control the imaging system. I also address how a real-time image compression scheme implemented on an FPGA chip speeds up image transfer speeds of the imaging system. Since lossless compression of the image is required in order to retain all image details, I began with an …
First Order Sigma-Delta Modulator Of An Oversampling Adc Design In Cmos Using Floating Gate Mosfets, Syam Prasad Sbs Kommana
First Order Sigma-Delta Modulator Of An Oversampling Adc Design In Cmos Using Floating Gate Mosfets, Syam Prasad Sbs Kommana
LSU Master's Theses
We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.
Survivable Multicasting In Wdm Optical Networks, Sateesh Chandra Shekhar
Survivable Multicasting In Wdm Optical Networks, Sateesh Chandra Shekhar
LSU Master's Theses
Opportunities abound in the global content delivery service market and it is here that multicasting is proving to be a powerful feature. In WDM networks, optical splitting is widely used to achieve multicasting. It removes the complications of optical-electronic-optical conversions [1]. Several multicasting algorithms have been proposed in the literature for building light trees. As the amount of fiber deployment increases in networks, the risk of losing large volumes of data traffic due to a fiber span cut or due to node failure also increases. In this thesis we propose heuristic schemes to make the primary multicast trees resilient to …
An Evaluation Of Multiple Branch Predictor And Trace Cache Advanced Fetch Unit Designs For Dynamically Scheduled Superscalar Processors, Slade S. Maurer
An Evaluation Of Multiple Branch Predictor And Trace Cache Advanced Fetch Unit Designs For Dynamically Scheduled Superscalar Processors, Slade S. Maurer
LSU Master's Theses
Semiconductor feature size continues to decrease permitting superscalar microprocessors to continue to increase the number of functional units available for execution. As the instruction issue width increases beyond the five instruction average basic block size of integer programs, more than one basic block must be issued per cycle to continue to increase instructions per cycle (IPC) performance. Researchers have created methods of fetching instructions beyond the first taken branch to overcome the bottleneck created by the limitations of conventional single branch predictors. We compare the performance of the multiple branch prediction (MBP) and trace cache (TC) fetch unit optimization methods. …
Watermarking Using Decimal Sequences, Navneet Kumar Mandhani
Watermarking Using Decimal Sequences, Navneet Kumar Mandhani
LSU Master's Theses
This thesis introduces the use of decimal sequences in watermarking to hide information for authentication. The underlying system is based on code division multiple access (CDMA), which is a form of spread spectrum communication. Different algorithms for the use of decimal sequences have been formulated for use in black and white images. The watermark is spread across the carrier image by using the d- sequences of optimal period and retrieval is made by the use of correlation. Matlab version 6.5 was used to implement the algorithms discussed in this thesis. The advantage of using d-sequences over PN sequences is that …