Engineering Commons^™

Design Of Cmos Four-Quadrant Gilbert Cell Multiplier Circuits In Weak And Moderate Inversion, Craig Timothy Remund

Theses and Dissertations

This thesis presents four-quadrant CMOS current-mode multiplier architectures based on the bipolar Gilbert cell multiplier architecture. Multipliers are designed using the CMOS subthreshold region to take advantage of the subthreshold exponential I-V relationship that closely matches bipolar modeling. It is discovered that biasing to remove drift current components and to address higher order effects such as ideality factor mismatch, threshold mismatch, body effect, and short channel effects, is important to provide a linear multiplier. It is also shown that distortion caused by device size mismatch and offset input currents can be used to cancel the distortion introduced by drift currents …

Design And Analysis Of Charge-Transfer Amplifiers For Low-Power Analog-To-Digital Converter Applications, William Joel Marble

Theses and Dissertations

The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion.

First, an analysis methodology is proposed which leads to a deterministic model of the voltage transfer function. The model is generalized to any timing scheme and can be extended to account for nonlinear threshold modulation. The model …

Design Of A High Speed Mixed Signal Cmos Mutliplying Circuit, David Ray Bartholomew

Theses and Dissertations

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.

Integrated Microbattery Charger For Autonomous Systems, Brian W. Lefevre

Theses and Dissertations

This thesis presents a microbattery recharging circuit suitable for autonomous microsystems. The battery charger chosen for this design is a constant current battery charger. Two methods of regulating the constant-current are discussed. A published shunt regulator design is analyzed and is presented with enhancements to the design. A series regulator that controls the current to the battery with a switch is designed and fabricated in a 1.5µm CMOS process. The fabricated prototype occupies less than 2.20x2.20mm and is expected to dissipate less than 25µW of power. A discrete model of the integrated circuit is constructed and tested to demonstrate that …