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Phase Locked Loop Using Vlsi Technology: A Bibliometric Survey And Future Research Directions, Ujwala Kshirsagar, Ayushi Kamboj Ms.

Library Philosophy and Practice (e-journal)

: For the design of high frequency networks power has been one of the most significant specifications. Power usage is therefore one of the most significant challenges to microprocessor design. If we lower the supply voltage, this immediately leads to a decrease in static and dynamic power usage in order to reduce the circuit's power dissipation. Decreasing the voltage of the supply, however, often decreases the circuit's output, which is not reasonable.

The low power proposed phase locked loop (PLL) is therefore built using microwind 3.1, 45nm CMOS/VLSI technology, which, in practice, at low power, delivers high intensity output. The …