Engineering Commons^™

Integrated Circuit Metrology By Multilevel Patterning Technology, Li Jiang

LSU Doctoral Dissertations

A low cost, high accuracy method is described in detail for measuring image placement in integrated circuit manufacture. The method measures both the overlay between levels and the absolute placement of features in a single level. The overlay is measured by a technique which views multiple levels separately. The absolute distances between features on a test wafer are measured by comparing the features to precision gratings. Optical imaging techniques are described for viewing and analyzing the grating images, as well as for measuring distortions in the observing microscope and a video camera. These techniques permit image placement measurements to be …