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Full-Text Articles in Engineering
Eliminating Via-Plane Coupling Using Ground Vias For High-Speed Signal Transitions, Songping Wu, Xin Chang, Christian Schuster, Xiaoxiong Gu, Jun Fan
Eliminating Via-Plane Coupling Using Ground Vias For High-Speed Signal Transitions, Songping Wu, Xin Chang, Christian Schuster, Xiaoxiong Gu, Jun Fan
Electrical and Computer Engineering Faculty Research & Creative Works
When a high-speed signal transits through a via that penetrates a plane pair, parallel-plane resonances can cause additional insertion loss for the signal. To eliminate this via-plane coupling, ground vias are added adjacent to the signal via. This paper discusses the impact of the ground vias as a function of the number of the ground vias, their locations, and the size of the plane pair. A block-by-block physics-based equivalent circuit modeling approach is used in the study. The underlying physics of the phenomenon and the design implications are also discussed in the paper.
Application Of Transmission Line Models To Backpanel Plated Through-Hole Via Design, Shaowei Deng, Todd H. Hubing, James L. Drewniak, Jun Fan, James L. Knighten, Norman W. Smith
Application Of Transmission Line Models To Backpanel Plated Through-Hole Via Design, Shaowei Deng, Todd H. Hubing, James L. Drewniak, Jun Fan, James L. Knighten, Norman W. Smith
Electrical and Computer Engineering Faculty Research & Creative Works
This paper introduces an approach of using a plated through-hole (PTH) via transmission-line model in the design of a thick printed circuit board, such as a backpanel. Full wave FEM modeling of a section of backpanel containing a differential via pair was compared with a transmission model. Computed values of the differential transmission loss agreed within an acceptable range for engineering studies, yet the transmission line model results required less than 2% of the computation time that the full wave model required. Effects of via spacing, via diameter and trace thickness were also examined.
Validation Of Equivalent Circuits Extracted From S-Parameter Data For Eye-Pattern Evaluation, Giuseppe Selli, Mauro Lai, Shaofeng Luan, James L. Drewniak, Richard E. Dubroff, Jun Fan, James L. Knighten, Norman W. Smith, Giulio Antonini, Antonio Orlandi, Bruce Archambeault, Samuel R. Connor
Validation Of Equivalent Circuits Extracted From S-Parameter Data For Eye-Pattern Evaluation, Giuseppe Selli, Mauro Lai, Shaofeng Luan, James L. Drewniak, Richard E. Dubroff, Jun Fan, James L. Knighten, Norman W. Smith, Giulio Antonini, Antonio Orlandi, Bruce Archambeault, Samuel R. Connor
Electrical and Computer Engineering Faculty Research & Creative Works
S-parameter circuit model extraction is usually characterized by a trade off between accuracy and complexity. Trading one feature for another may or may not affect the goodness of the reconstructed S-parameter data, which are obtained from frequency domain simulations of the models extracted. However, the ultimate test for the validity of these equivalent circuit representations should be left to eye-diagram simulations, which provide useful insights, from an SI point of view, about the degradation of the signal, as it travels through the system. Physics based simplication procedures can be used to tune the models and achieve less complexity, whereas the …
Extracting R, L, G, C Parameters Of Dispersive Planar Transmission Lines From Measured S-Parameters Using A Genetic Algorithm, Jianmin Zhang, Marina Koledintseva, James L. Drewniak, Giulio Antonini, Antonio Orlandi, Konstantin Rozanov
Extracting R, L, G, C Parameters Of Dispersive Planar Transmission Lines From Measured S-Parameters Using A Genetic Algorithm, Jianmin Zhang, Marina Koledintseva, James L. Drewniak, Giulio Antonini, Antonio Orlandi, Konstantin Rozanov
Electrical and Computer Engineering Faculty Research & Creative Works
Signal integrity (SI) analysis of printed circuit boards for high-speed digital design requires information on the perunit-length R, L, G, C parameters of the transmission lines. However, these are not always available when the property of the dielectric medium used in the board is unknown. A method to extract R, L, G, and C parameters from parallel-plate and strip transmission line geometries is proposed. It is based on measured scattering parameters and analytical modeling. A genetic algorithm (GA) is used to optimize the extraction by minimizing the frequency domain discrepancy between an objective function, which is the measured scattering matrix …
Extraction Of A Spice Via Model From Full-Wave Modeling For Differential Signaling, Shaofeng Luan, Giuseppe Selli, James L. Drewniak, Andrea De Luca, Giulio Antonini, Antonio Orlandi, Antonio Ciccomancini Scogna, Jun Fan, James L. Knighten, Norman W. Smith, Ray Alexander
Extraction Of A Spice Via Model From Full-Wave Modeling For Differential Signaling, Shaofeng Luan, Giuseppe Selli, James L. Drewniak, Andrea De Luca, Giulio Antonini, Antonio Orlandi, Antonio Ciccomancini Scogna, Jun Fan, James L. Knighten, Norman W. Smith, Ray Alexander
Electrical and Computer Engineering Faculty Research & Creative Works
This paper presents a procedure for building SPICE models for via transitions in differential signaling. The method of extracting parameters of SPICE models from a full-wave simulation tool is demonstrated. Then the validity of the SPICE models is studied by comparing the solution from the SPICE models with that from the full-wave simulation.
A Study On The Correspondence Of Common-Mode Current In Electromagnetic Radiation From A Pcb With A Guard-Band, Yoshiki Kayano, Motoshi Tanaka, Hiroshi Inoue, James L. Drewniak
A Study On The Correspondence Of Common-Mode Current In Electromagnetic Radiation From A Pcb With A Guard-Band, Yoshiki Kayano, Motoshi Tanaka, Hiroshi Inoue, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
A PCB, in which the ground plane has a finite width and the trace has unbalanced positioning, can result in common-mode (CM) radiation. So far, CM current which is generated by the unbalance of a trace and ground plane has been investigated by experiment and numerical method. It was clarified that CM current is well explained the radiation from PCB up to a few hundred megahertz, and addition of a guard band geometry, which is well connected to the ground plane, can be effective in suppressing the CM current. But it is seemed to be insufficient description for the phenomena …
Effects Of Open Stubs Associated With Plated Through-Hole Vias In Backpanel Designs, Shaowei Deng, Jingkun Mao, Todd H. Hubing, James L. Drewniak, Jun Fan, James L. Knighten, Norman W. Smith, Ray Alexander, Chen Wang
Effects Of Open Stubs Associated With Plated Through-Hole Vias In Backpanel Designs, Shaowei Deng, Jingkun Mao, Todd H. Hubing, James L. Drewniak, Jun Fan, James L. Knighten, Norman W. Smith, Ray Alexander, Chen Wang
Electrical and Computer Engineering Faculty Research & Creative Works
Plated through-hole (PTH) vias are commonly used in printed circuit boards. They usually leave open stubs if the signal(s) does not transition the entire depth of the board. These open stubs can have a negative impact on signal transmission. This summary reports the investigation of the impact of the open via stubs in a typical backpanel design.
Memory Dimm Dc Power Distribution Analysis And Design, Jingkun Mao, Chen Wang, Giuseppe Selli, Bruce Archambeault, James L. Drewniak
Memory Dimm Dc Power Distribution Analysis And Design, Jingkun Mao, Chen Wang, Giuseppe Selli, Bruce Archambeault, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
DC power bus design is critical in meeting signal integrity (SI) and electromagnetic compatibility (EMC) requirements. A suitable modeling tool is beneficial to evaluate power bus design and develop design guidelines. This paper discusses difficulties met in evaluating the power distribution design on a dual inline memory module (DIMM) board, such as a power bus with arbitrary shape, parasitic inductance associated with vias, and so on. Moreover, some solutions are given in this paper. A simple cavity model with a segmentation method was employed to model a power bus with irregular shapes. The partial element equivalent circuit (PEEC) technique was …
Anticipating Emi Using Transfer Functions And Signal Integrity Information, Chen Wang, James L. Drewniak, Jim Nadolny
Anticipating Emi Using Transfer Functions And Signal Integrity Information, Chen Wang, James L. Drewniak, Jim Nadolny
Electrical and Computer Engineering Faculty Research & Creative Works
Discontinuities in a circuit can lead to signal integrity as well as EMI problems. A method, which efficiently combines full-wave tools and circuit simulators, is proposed herein to analyze the coupling at discontinuities. The proposed method may be applied to practical engineering designs.
Dc Power-Bus Noise Isolation With Power-Plane Segmentation, Wei Cui, Jun Fan, Yong Ren, Hao Shi, James L. Drewniak, Richard E. Dubroff
Dc Power-Bus Noise Isolation With Power-Plane Segmentation, Wei Cui, Jun Fan, Yong Ren, Hao Shi, James L. Drewniak, Richard E. Dubroff
Electrical and Computer Engineering Faculty Research & Creative Works
Power-plane segmentation is often used for DC power-bus noise isolation in multilayer printed circuit board (PCB) designs. To achieve a desirable noise isolation, different power-plane segmentations can be used. A suitable modeling approach, as well as measurements, were employed in this work to study the noise isolation with several power-plane segmentation designs. The geometries studied include power islands, and totally segmented power planes. The effects of the power-bus noise isolation with different types of power island connections, locations of segmentation, and shapes were analyzed, and compared. The modeled and measured results show that suitable power-plane segmentation can result in significant …
Lumped-Circuit Model Extraction For Vias In Multilayer Substrates, Jun Fan, James L. Drewniak, James L. Knighten
Lumped-Circuit Model Extraction For Vias In Multilayer Substrates, Jun Fan, James L. Drewniak, James L. Knighten
Electrical and Computer Engineering Faculty Research & Creative Works
Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted …
Power-Bus Decoupling With Embedded Capacitance In Printed Circuit Board Design, Minjia Xu, Todd H. Hubing, Juan Chen, Thomas Van Doren, James L. Drewniak, Richard E. Dubroff
Power-Bus Decoupling With Embedded Capacitance In Printed Circuit Board Design, Minjia Xu, Todd H. Hubing, Juan Chen, Thomas Van Doren, James L. Drewniak, Richard E. Dubroff
Electrical and Computer Engineering Faculty Research & Creative Works
This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire …
Estimating The Noise Mitigation Effect Of Local Decoupling In Printed Circuit Boards, Jun Fan, Wei Cui, James L. Drewniak, Thomas Van Doren, James L. Knighten
Estimating The Noise Mitigation Effect Of Local Decoupling In Printed Circuit Boards, Jun Fan, Wei Cui, James L. Drewniak, Thomas Van Doren, James L. Knighten
Electrical and Computer Engineering Faculty Research & Creative Works
Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bus noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are …
Power Bus Isolation Using Power Islands In Printed Circuit Boards, J. Chen, Todd H. Hubing, Richard E. Dubroff, Thomas Van Doren
Power Bus Isolation Using Power Islands In Printed Circuit Boards, J. Chen, Todd H. Hubing, Richard E. Dubroff, Thomas Van Doren
Electrical and Computer Engineering Faculty Research & Creative Works
Power islands are often employed in printed circuit board (PCB) designs to alleviate the problem of power bus noise coupling between circuits. Good isolation can be obtained over a wide frequency band due to the large series impedance provided by the gap between the power islands. However, power bus resonances may degrade the isolation at high frequencies. The amount of isolation also depends on the type of connection between power islands and the components on the board. This paper experimentally investigates the effectiveness of several power island structures up to 3.0 GHz
Reducing Power Bus Impedance At Resonance With Lossy Components, Todd H. Hubing, Theodore M. Zeeff
Reducing Power Bus Impedance At Resonance With Lossy Components, Todd H. Hubing, Theodore M. Zeeff
Electrical and Computer Engineering Faculty Research & Creative Works
Power bus structures in printed circuit boards with solid power and ground planes exhibit resonances. When the power bus is resonant, the power bus impedance can increase dramatically. This paper explores the effect of component equivalent series resistance (ESR) on power bus resonances. General guidelines for selecting an optimum ESR are provided and are supported by laboratory measurements and numerical simulations.
Dc Power-Bus Modeling And Design With A Mixed-Potential Integral-Equation Formulation And Circuit Extraction, Jun Fan, James L. Drewniak, Hao Shi, James L. Knighten
Dc Power-Bus Modeling And Design With A Mixed-Potential Integral-Equation Formulation And Circuit Extraction, Jun Fan, James L. Drewniak, Hao Shi, James L. Knighten
Electrical and Computer Engineering Faculty Research & Creative Works
Application of a circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) for dc power-bus modeling in high-speed digital designs is detailed herein. Agreement with measurements demonstrates the effectiveness of the approach. Dielectric losses are included into the calculation of Green's functions, and thus, incorporated into the rigorous first principles formulation. A SPICE model is then extracted from the discretized integral equation. A quasistatic approximation is used for Green's functions to keep the extracted circuit elements frequency independent. Previous work has established a necessary meshing criterion in order to ensure accuracy for a given substrate thickness and dielectric …
Including Smt Ferrite Beads In Dc Power Bus And High-Speed I/O Line Modeling, Jun Fan, Shaofeng Luan, James L. Drewniak
Including Smt Ferrite Beads In Dc Power Bus And High-Speed I/O Line Modeling, Jun Fan, Shaofeng Luan, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
Surface mount technology (SMT) ferrite beads are often used in high-speed digital circuit designs to mitigate noise. The common modeling approach is to include SMT ferrite beads as equivalent lumped LCR circuits. The work presented in this paper included SMT ferrite beads as a frequency-dependent impedance in a PEEC-like modeling tool denoted CEMPIE, a circuit extraction approach based on a mixed-potential integral equation formulation. Agreement with measurements demonstrates the approach. The applications shown are segmentation of power areas for noise isolation, and I/O line filtering.
Modeling Dc Power-Bus Structures With Vertical Discontinuities Using A Circuit Extraction Approach Based On A Mixed-Potential Integral Equation, Jun Fan, Hao Shi, Antonio Orlandi, James L. Knighten, James L. Drewniak
Modeling Dc Power-Bus Structures With Vertical Discontinuities Using A Circuit Extraction Approach Based On A Mixed-Potential Integral Equation, Jun Fan, Hao Shi, Antonio Orlandi, James L. Knighten, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green's functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design.
Dc Power Bus Design With Fdtd Modeling Including A Dispersive Media, Xiaoning Ye, Jun Fan, Marina Koledintseva, James L. Drewniak
Dc Power Bus Design With Fdtd Modeling Including A Dispersive Media, Xiaoning Ye, Jun Fan, Marina Koledintseva, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
DC power-bus modeling in high-speed digital design using the FDTD method is reported here. The dispersive medium is approximated by a Debye model to account for the loss. A wide band frequency response (100 MHz-5 GHz) is obtained through a single FDTD simulation. Favorable agreement is achieved between the modeled and measured results for a typical DC power-bus structure with multiple SMT decoupling capacitors mounted on the board. The FDTD tool is then applied to investigate the effects of local decoupling on a DC power-bus. The modeled results agree with the results from another modeling tool, the CEMPIE (a circuit …
Fdtd And Fem/Mom Modeling Of Emi Resulting From A Trace Near A Pcb Edge, Daniel P. Berg, Motoshi Tanaka, Yun Ji, Xiaoning Ye, James L. Drewniak, Todd H. Hubing, Richard E. Dubroff, Thomas Van Doren
Fdtd And Fem/Mom Modeling Of Emi Resulting From A Trace Near A Pcb Edge, Daniel P. Berg, Motoshi Tanaka, Yun Ji, Xiaoning Ye, James L. Drewniak, Todd H. Hubing, Richard E. Dubroff, Thomas Van Doren
Electrical and Computer Engineering Faculty Research & Creative Works
PCB traces routed near board edges and carrying high-speed signals are considered to contribute to EMI problems. Consequently, design maxims state that traces that might have intentional or unintentional high frequency components on them be kept away from board edges. This costs valuable surface area as boards become more densely designed. Further, design maxims concerning traces near board edges are not well quantified. The increase in EMI as a trace is routed increasingly closer to the PCB edge has been studied experimentally and with numerical modeling.
Development Of A Closed-Form Expression For The Input Impedance Of Power-Ground Plane Structures, Minjia Xu, Yun Ji, Todd H. Hubing, Thomas Van Doren, James L. Drewniak
Development Of A Closed-Form Expression For The Input Impedance Of Power-Ground Plane Structures, Minjia Xu, Yun Ji, Todd H. Hubing, Thomas Van Doren, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
This paper analyzes the fundamental behavior of PCB power bus structures using the modal expansion method. The results are validated by experiments and full-wave numerical modeling. It is shown that the power bus can be modeled as a series LeC circuit below the first board resonance frequency. C is the interplane capacitance and Le is an effective inductance contributed by all the cavity nodes. The effects of the layer thickness, port location, board size and the feeding wire radius on the value of Le are discussed in this study. Le can be estimated from the …
Emi Resulting From A Signal Via Transition Through Dc Power Bus-Effectiveness Of Focal Smt Decoupling, Wei Cui, Xiaoning Ye, Bruce Archambeault, Doug White, Min Li, James L. Drewniak
Emi Resulting From A Signal Via Transition Through Dc Power Bus-Effectiveness Of Focal Smt Decoupling, Wei Cui, Xiaoning Ye, Bruce Archambeault, Doug White, Min Li, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
Signal vias are commonly used in multilayer printed circuit board (PCB) design. For a signal via transitioning through the internal power and ground planes, the return current has to jump from one reference plane to another reference plane. The discontinuity of the return current at the via excites the power and ground planes, and results in power bus noise, and can produce an EMI problem as well. Numerical methods, such as finite-difference time-domain (FDTD), moment methods (MoM), and partial element equivalent circuit (PEEC), were employed herein to study this problem. The modeled results were supported by the measurements. In addition, …
Modeling Emi Resulting From A Signal Via Transition Through Power/Ground Layers, Wei Cui, Xiaoning Ye, Bruce Archambeault, Doug White, Min Li, James L. Drewniak
Modeling Emi Resulting From A Signal Via Transition Through Power/Ground Layers, Wei Cui, Xiaoning Ye, Bruce Archambeault, Doug White, Min Li, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
Signal transitioning through layers on vias are very common in multi-layer printed circuit board (PCB) design. For a signal via transitioning through the internal power and ground planes, the return current must switch from one reference plane to another reference plane. The discontinuity of the return current at the via excites the power and ground planes, and results in noise on the power bus that can lead to signal integrity, as well as EMI problems. Numerical methods, such as the finite-difference time-domain (FDTD), Moment of Methods (MoM), and partial element equivalent circuit (PEEC) method, were employed herein to study this …
Signal Induced Emi In Fibre Channel Cable-Connector Assemblies, Minjia Xu, S. Radu, James L. Knighten, James L. Drewniak, Todd H. Hubing, L. O. Hoeft, J. T. Dibene Ii
Signal Induced Emi In Fibre Channel Cable-Connector Assemblies, Minjia Xu, S. Radu, James L. Knighten, James L. Drewniak, Todd H. Hubing, L. O. Hoeft, J. T. Dibene Ii
Electrical and Computer Engineering Faculty Research & Creative Works
The EMI performance of cable-connector assemblies designed for FC-0 transmission has been studied. Two types of cable and two connector styles were evaluated. Experimental results show that the dominant radiation mechanism for short cable lengths is the common-mode current caused by source and PCB skew that leaks to the exterior of the shield via the transfer impedance of the connector. However, the cable imbalance becomes a more significant source of common-mode current than the source skew when the cable assembly is tens of meters long.
Rf Isolation Using Power Islands In Dc Power Bus Design, Jun Fan, Yong Ren, Juan Chen, David M. Hockanson, Hao Shi, James L. Drewniak, Todd H. Hubing, Thomas Van Doren, Richard E. Dubroff
Rf Isolation Using Power Islands In Dc Power Bus Design, Jun Fan, Yong Ren, Juan Chen, David M. Hockanson, Hao Shi, James L. Drewniak, Todd H. Hubing, Thomas Van Doren, Richard E. Dubroff
Electrical and Computer Engineering Faculty Research & Creative Works
Power island structures are often employed for minimizing the propagation of high-frequency noise on DC power buses. The rationale is based on introducing a series impedance in the power plane to provide isolation of a noise source from the rest of the PCB design. The power island concept is investigated herein experimentally, to determine its noise mitigation attributes and limitations. A modeling approach that is suitable for arbitrary PCB island geometries including lumped SMT decoupling capacitors is also presented. The modeling and measurements indicate that island structures can achieve some degree of isolation under certain conditions.
Power Bus Noise Reduction Using Power Islands In Printed Circuit Board Designs, Todd H. Hubing, Juan Chen, James L. Drewniak, Thomas Van Doren, Y. Ren, Jun Fan, Richard E. Dubroff
Power Bus Noise Reduction Using Power Islands In Printed Circuit Board Designs, Todd H. Hubing, Juan Chen, James L. Drewniak, Thomas Van Doren, Y. Ren, Jun Fan, Richard E. Dubroff
Electrical and Computer Engineering Faculty Research & Creative Works
Power islands are often used to isolate devices that put noise on a power bus from devices that may be susceptible to power bus noise. At high frequencies however, the effectiveness of these islands depends on the implementation. This paper experimentally investigates the effectiveness of different power island structures at frequencies up to 3 GHz.
Incorporating Vertical Discontinuities In Power-Bus Modeling Using A Mixed-Potential Integral Equation And Circuit Extraction Formulation, Jun Fan, Hao Shi, James L. Drewniak, Todd H. Hubing, Richard E. Dubroff, Thomas Van Doren
Incorporating Vertical Discontinuities In Power-Bus Modeling Using A Mixed-Potential Integral Equation And Circuit Extraction Formulation, Jun Fan, Hao Shi, James L. Drewniak, Todd H. Hubing, Richard E. Dubroff, Thomas Van Doren
Electrical and Computer Engineering Faculty Research & Creative Works
Noise on the DC power-bus attributed to device switching is among the primary sources of EMI and signal integrity problems. A mixed-potential integral equation formulation with circuit extraction approach is used to model the planar multi-layer power-bus geometry, which can also include arbitrary shaped power regions on multiple layers. Incorporating vertical discontinuities, e.g., decoupling capacitor interconnects, is a critical aspect of the modeling, and must be done properly since they are included as a lumped element model and not a part of the MPIE formulation. Agreement with experimental results demonstrate the present approach.
Modeling Multilayered Pcb Power-Bus Designs Using An Mpie Based Circuit Extraction Technique, Hao Shi, Jun Fan, James L. Drewniak, Todd H. Hubing, Thomas Van Doren
Modeling Multilayered Pcb Power-Bus Designs Using An Mpie Based Circuit Extraction Technique, Hao Shi, Jun Fan, James L. Drewniak, Todd H. Hubing, Thomas Van Doren
Electrical and Computer Engineering Faculty Research & Creative Works
A circuit extraction tool (CEMPIE) has been developed based on the mixed-potential integral equation (MPIE) using a quasi-static approximation. A power-bus in a multi-layered PCB consisting of a pair of dedicated ground and power planes is studied using this tool. The distributed behavior of a power-bus is represented by a collection of passive circuit elements, which is valid up to several gigahertz. The decoupling performance of a power-bus due to its layer spacing and the dielectric constant is evaluated for simple test geometries. The impact of the relative distance between the noise source and the potential receiver is also studied. …
Investigation Of Split Groundplanes At The Connector For Emi Control, David M. Hockanson, James L. Drewniak, Joe Nuebel, James C. Parker Jr.
Investigation Of Split Groundplanes At The Connector For Emi Control, David M. Hockanson, James L. Drewniak, Joe Nuebel, James C. Parker Jr.
Electrical and Computer Engineering Faculty Research & Creative Works
EMI can often be reduced by selectively filtering various parts of a given system. One common method employed by designers is to split the groundplane near the chassis and route I/O lines over the split. The rationale is based on providing a large series impedance to common-mode currents on the I/O lines. In this manner, PCB designers hope to lower the level of noise currents contributing to radiation. This work studies the efficacy of the groundplane split as a deterrent for EMI associated with I/O lines being driven against other extended reference structures. A test-board was developed to analyze the …
Investigation Of Fundamental Emi Source Mechanisms Driving Common-Mode Radiation From Printed Circuit Boards With Attached Cables, David M. Hockanson, James L. Drewniak, Todd H. Hubing, Thomas Van Doren, Fei Sha, Michael J. Wilhelm
Investigation Of Fundamental Emi Source Mechanisms Driving Common-Mode Radiation From Printed Circuit Boards With Attached Cables, David M. Hockanson, James L. Drewniak, Todd H. Hubing, Thomas Van Doren, Fei Sha, Michael J. Wilhelm
Electrical and Computer Engineering Faculty Research & Creative Works
Fundamental EMI source mechanisms leading to common-mode radiation from printed circuit boards with attached cables are presented in this paper. Two primary EMI source mechanisms have been identified: one associated with a differential-mode voltage and another associated with a differential-mode current, both of which result in a common-mode current on an attached cable. These mechanisms can be used to relate printed circuit layout geometries to EMI sources. The two mechanisms are demonstrated through numerical and experimental results, and an example from a production printed-circuit design is presented.