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Faulty Behavior Of Storage Elements And Its Effects On Sequential Circuits, Waleed K. Al-Assadi, Y. K. Malaiya, A. P. Jayasumana
Faulty Behavior Of Storage Elements And Its Effects On Sequential Circuits, Waleed K. Al-Assadi, Y. K. Malaiya, A. P. Jayasumana
Electrical and Computer Engineering Faculty Research & Creative Works
It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault …
Modeling Of Intra-Cell Defects In Cmos Sram, Waleed K. Al-Assadi, Y. K. Malaiya, A. P. Jayasumana
Modeling Of Intra-Cell Defects In Cmos Sram, Waleed K. Al-Assadi, Y. K. Malaiya, A. P. Jayasumana
Electrical and Computer Engineering Faculty Research & Creative Works
The effect of defects within a single cell of a static random access memory (SRAM) is examined. All major types of faults, including bridging, transistor stuck-open and stuck-on, are examined. A significant fraction of all faults cause high IDDQ values to be observed. Faults leading to inter-cell coupling are identified.