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A Finite State Machine Synthesizer, Jiuling Liu
A Finite State Machine Synthesizer, Jiuling Liu
Dissertations and Theses
This thesis presents a Finite State Machine (FSM) Synthesizer developed at Portland State University. The synthesizer starts from a high level behavioral description, in which no states are specified, and generates the lower level FSM descriptions for simulation and physical layout generation.
A New Approach To State Minimization Of Finite State Machines, William Yue Zhao
A New Approach To State Minimization Of Finite State Machines, William Yue Zhao
Dissertations and Theses
A complete program to ease the task of large scale Finite State Machine (FSM) minimization presented in this thesis: TDFM (Two Dimensional FSM Minimizer), is a part of the DIADES system. DIADES is an Automatic Design Synthesis System whose development in the Department of Electrical Engineering at Portland State University is supported in part by a research grant from SHARP Microelectronics Technology.