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Limiting And Transient Performances Of A Low Loss Pin-Schottky Limiter, Chin-Leong Lim

Chin-Leong Lim

The main cause of loss in the PIN-Schottky limiter is the diodes’ parasitic capacitances. Techniques to counter the parasitic capacitances include using bare chip, air cavity packaging, diode stacking, mesa construction, isolating the Schottky diode from the signal path and connecting the diodes to a low impedance node. But the aforementioned techniques either sacrifice cost, manufacturability, size, performances or thermal ruggedness. To reduce loss in the PIN-Schottky limiter, we re-configured its parasitics into a low pass ladder network. This paper reports on the new configuration’s changed large signal and transient performances. We observed improved isolation at 0.9 and 2.4 GHz, …