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Fpga Design Of A Hardware Efficient Pipelined Fft Processor, Ryan T. Bone

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Digital receivers involve fast Fourier transform (FFT) computations that require a large amount of arithmetic operations. The implementation of a FFT processor is one of the most challenging parts in the realization of a wideband receiver and its hardware complexity is very high. Hence, kernel function FFT processors have been proposed to meet real-time processing requirements and to reduce hardware complexity by rounding the kernel function to predetermined kernel points so as to eliminate the multipliers and use only shifters and adders or subtractors. Because of the nonlinear nature of this approximation by the rounding errors, spurious responses are generated …