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Full-Text Articles in Engineering
Runtime Detection Of A Bandwidth Denial Attack From A Rogue Network-On-Chip, Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Runtime Detection Of A Bandwidth Denial Attack From A Rogue Network-On-Chip, Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
In this paper, we propose a covert threat model for MPSoCs designed using 3rd party Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for the software running on the MPSoC platform. We then propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. For the proposed technique, our comprehensive cross-layer analysis indicates modest overheads of 12.73% in area, 9.844% in power and 5.4% in terms of network latency.
Tackling Voltage Emergencies In Noc Through Timing Error Resilience., Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Tackling Voltage Emergencies In Noc Through Timing Error Resilience., Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency.
Design Of Reliable And Secure Network-On-Chip Architectures, Dean Michael B Ancajas
Design Of Reliable And Secure Network-On-Chip Architectures, Dean Michael B Ancajas
All Graduate Theses and Dissertations, Spring 1920 to Summer 2023
The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues. This dissertation demonstrates design techniques that address both reliability and security issues facing modern NoC architectures. The reliability and security problem is tackled at different abstraction levels using a series of schemes that combine information from the architecture-level as well as hardware-level in order to combat aging effects and meet secure design stipulations while maintaining modest power-performance overheads.