Engineering Commons^™

Voltage Scaled Low Power Dnn Accelerator Design On Reconfigurable Platform, Rourab Paul, Sreetama Sarkar, Suman Sau, Sanghamitra Roy, Koushik Chakraborty, Amlan Chakrabarti

Electrical and Computer Engineering Faculty Publications

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of …