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Trident: A Comprehensive Timing Error Resilient Technique Against Choke Points At Ntc., Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
Trident: A Comprehensive Timing Error Resilient Technique Against Choke Points At Ntc., Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
Electrical and Computer Engineering Faculty Publications
Near Threshold Computing (NTC) systems have been inherently plagued with heightened process variation (PV) sensitivity. Choke points are an intriguing manifestation of this PV sensitivity. In this paper, we explore the probability of minimum timing violations, caused by choke points, in an NTC system and, their non-Trivial impacts on the system reliability. We show that conventional timing error mitigation techniques are inefficient in tackling choke point induced minimum timing violations. Consequently, we propose a comprehensive error mitigation technique, Trident, to tackle choke points, at NTC. Trident offers a 1.37x performance improvement and a 1.1x energy efficiency gain over Razor at …
Dynamic Choke Sensing For Timing Error Resilience In Ntc Systems, Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty
Dynamic Choke Sensing For Timing Error Resilience In Ntc Systems, Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty
Electrical and Computer Engineering Faculty Publications
Process variation (PV) is a conspicuous predicament for submicrometer VLSI circuits. In this paper, we illustrate "choke points" as a vital consequence of PV in the near-threshold computing domain. Choke points are PV affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths postfabrication. To mitigate the timing errors induced thereby, we propose dynamic choke sensing (DCS). This technique senses the timing error causing opcode sequences, and uses the knowledge to prevent similar sequences from causing errors in the future. We propose two variants of our scheme. Our techniques provide ~55% improvement in performance and …