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Simncore: Multilevel Cache Memory Design Simulator For Manycore System, Provashish Roy
Simncore: Multilevel Cache Memory Design Simulator For Manycore System, Provashish Roy
Theses and Dissertations
The current trend in a processor design has moved from multicore to manycore (tens to hundreds, or more cores) to support more computational power based on parallelism. One of challenges is how to handle such large number of cores’ data in cache memories through an efficient inter-core communication and cache coherence. To meet the demand, this paper presents a manycore cache memory simulator for research and education purposes. The proposed simulator, called as SIMNCORE, is to design and evaluate various multi-level, such as L1 and L2, cache memories for manycore processing. The SIMNCORE will implement various trace files collected from …