Engineering Commons^™

Static Compaction Of Test Sequences For Synchronous Sequential Circuits, Lijie Qi

Dissertations and Theses

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit.

Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length. compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length. the memory requirements during the test application and the test application time are reduced. …

Passive Circuit Modeling Using Ipa510, Hassan Hiwaidi Al-Sheikhly

Dissertations and Theses

Characterizing the high speed interconnect performance of circuit board, integrated circuit packages and multichip module become very important when the clock frequencies in digital and RF systems become larger than 200 MHz. At time scales less than 2 ns distributed approach must be used to measure package parasitics (stray inductance and capacitance) and transmission line effects.

A practical way to measure and model the package parasitics is by utilizing Interconnect Parameter Analyzer (IP A510). The IP A510 uses Time Domain Reflectometry (TDR) technique. The TDR technique is based on sending a waveform to a device under test (DUT) and capturing …

An Approach To Exact Modeling Of The Pwm Switch, Anas N. Al-Rabadi

Dissertations and Theses

Large number of small-signal models of de-to-de power converters exists already. These models usually use two techniques. The first is the averaging technique, such as: volt-second and current-second balance, state space averaging, and the averaged modeling approach. The other technique focuses on the exact modeling approach, such as: the application of time varying systems theory to linearize networks. One of the methodologies to apply the above techniques, is to view the three-terminal systems as a two-port network.

The aim of the work presented in this thesis is to develop a new approach, by the application of the two-port network methodology …

The Design Of Cube Calculus Machine Using Sram-Based Fpga Reconfigurable Hardware Dec’S Perle-1 Board, Qihong Chen

Dissertations and Theses

Presented in this thesis are new approaches to column compatibility checking and column-based input/output encoding for Curtis decompositions of switching functions. These approaches can be used in Curtis-type functional decomposition programs for applications in several scientific disciplines. Examples of applications are: minimization of combinational and sequential logic) mapping of logic functions to programmable logic devices such as CPLDs, MPGAs, and FPGAs, data encryption, data compression, pattern recognition) and image refinement. Presently, Curtis-type functional decomposition programs are used primarily for experimental purposes due to performance, quality, and compatibility issues. However) in the past few years a renewal of interest in the …

Rtl Power Estimation Of Sequential Circuits, Sridhar Muthrasanallur

Dissertations and Theses

Power consumption has become a major concern in the electronic industry in recent years because of the increased demand for portable electronic devices. Part of the problem in power conscious design is accurate power estimation. Power estimation at low-levels of design abstraction is slow since the units of low-levels of design abstraction are transistors or gates. But designers need reliable power estimates early in the design process. Therefore designers need to have tools for fast and accurate power estimation at higher levels of design abstraction such as the Register Transfer Level (RTL).

This thesis introduces a new method for RTL …