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Full-Text Articles in Engineering
Semi-Modular Delay Model Revisited In Context Of Relative Timing, Hoon Park, Anping He, Marly Roncken, Xiaoyu Song
Semi-Modular Delay Model Revisited In Context Of Relative Timing, Hoon Park, Anping He, Marly Roncken, Xiaoyu Song
Electrical and Computer Engineering Faculty Publications and Presentations
A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuits is presented. While previous definitions ignore such constraints, the new definition takes them into account. The difference on a design solution for a well-known speed-independent circuit implementation of the Muller C element and a set of relative timing constraints that renders the implementation hazard free is illustrated. The old definition produces a false semi-modularity conflict that cannot exist due to the set of imposed constraints. The new definition correctly accepts the solution.
Logic Synthesis For Layout Regularity Using Decision Diagrams, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jinsong Zhang, Marek Perkowski
Logic Synthesis For Layout Regularity Using Decision Diagrams, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jinsong Zhang, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
This paper presents a methodology for logic synthesis of Boolean functions in the form of regular structures that can be mapped into standard cells or programmable devices. Regularity offers an elegant solution to hard problems arising in layout and test generation, at no extra cost or at the cost of increasing the number of gates, which does not always translate into the increase of circuit area. Previous attempts to synthesize logic into regular structures using decision diagrams suffered from an increase in the number of logic levels due to multiple repetitions of control variables. This paper proposes new techniques, which …
Logic Synthesis For Regular Fabric Realized In Quantum Dot Cellular Automata, Marek Perkowski, Alan Mishchenko
Logic Synthesis For Regular Fabric Realized In Quantum Dot Cellular Automata, Marek Perkowski, Alan Mishchenko
Electrical and Computer Engineering Faculty Publications and Presentations
Quantum Dot Cellular Automata are one of the most prospective nano-technologies to build digital circuits. Because of the requirements of only 2 layer wiring and noise avoidance, realizing the circuit in a regular fabrics is even more important for this technology than for classical technologies. In this paper, we propose a regular layout geometry called 3x3 lattice. The main difference of this geometry compared to the known 2x2 lattices is that it allows the cofactors on a level to propagate to three rather than two nodes on the lower level. This gives additional freedom to synthesize compact functional representations. We …
Function-Driven Linearly Independent Expansions Of Boolean Functions And Their Application To Synthesis Of Reversible Circuits, Pawel Kerntopf, Marek Perkowski
Function-Driven Linearly Independent Expansions Of Boolean Functions And Their Application To Synthesis Of Reversible Circuits, Pawel Kerntopf, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
The paper presents a family of new expansions of Boolean functions called Function-driven Linearly Independent (fLI) expansions. On the basis of this expansion a new kind of a canonical representation of Boolean functions is constructed: Function-driven Linearly Independent Binary Decision Diagrams (fLIBDDs). They generalize both Function-driven Shannon Binary Decision Diagrams (fShBDDs) and Linearly Independent Binary Decision Diagram (LIBDDs). The diagrams introduced in the paper, can provide significantly smaller representations of Boolean functions than standard Ordered Binary Decision Diagrams (OBDDs), Ordered Functional Decision Diagrams (OFDDs) and Ordered (Pseudo-) Kronecker Functional Decision Diagrams (OKFDDs) and can be applied to synthesis of reversible …
Multi-Output Esop Synthesis With Cascades Of New Reversible Gate Family, Mozammel H.A. Khan, Marek Perkowski
Multi-Output Esop Synthesis With Cascades Of New Reversible Gate Family, Mozammel H.A. Khan, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
A reversible gate maps each output vector into a unique input vector and vice versa. The importance of reversible logic lies in the technological necessity that most "near-future" and all long-term future technologies will have to use reversible gates in order to reduce power. In this paper, a new generalized k*k reversible gate family is proposed. A synthesis method for multi-output (factorized) ESOP using cascades of the new gate family is presented. For utilizing the benefit of product sharing among the ESOPs, two graph-based data structures -connectivity tree and implementation graph are used. Experimental results with some MCNC benchmark functions …
Logic Synthesis Of Reversible Wave Cascades, Alan Mishchenko, Marek Perkowski
Logic Synthesis Of Reversible Wave Cascades, Alan Mishchenko, Marek Perkowski
Electrical and Computer Engineering Faculty Publications and Presentations
A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible logic synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible logic synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation …
Implicit Algorithms For Multi-Valued Input Support Manipulation, Alan Mishchenko, Craig Files, Marek Perkowski, Bernd Steinbach, Christina Dorotska
Implicit Algorithms For Multi-Valued Input Support Manipulation, Alan Mishchenko, Craig Files, Marek Perkowski, Bernd Steinbach, Christina Dorotska
Electrical and Computer Engineering Faculty Publications and Presentations
We present an implicit approach to solve problems arising in decomposition of incompletely specified multi-valued functions and relations. We introduce a new representation based on binaryencoded multi-valued decision diagrams (BEMDDs). This representation shares desirable properties of MDDs, in particular, compactness, and is applicable to weakly-specified relations with a large number of output values. This makes our decomposition approach particularly useful for data mining and machine learning. Using BEMDDs to represent multi-valued relations we have developed two complementary input support minimization algorithms. The first algorithm is efficient when the resulting support contains almost all initial variables; the second is efficient when …