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Cost And Performance Modeling Of The Mu-Decoder, Raghavendra Kongari
Cost And Performance Modeling Of The Mu-Decoder, Raghavendra Kongari
LSU Master's Theses
In this thesis we study the implementation details of the MU-Decoders, a recently proposed hardware module that has been theoretically shown to be superior to other methods for generating subsets of large sets. Our study confirms this advantage. Specifically, we compare the performance of implementations of the LUT-Decoder (the most common configurable decoder) to the MU-Decoder. We show that for while the LUT-Decoder is slightly better than the MU-Decoder for arbitrary (and artificial) inputs, for a large class of inputs called totally ordered subsets, that have practical significance, the MU-Decoder is vastly superior in area to the LUT-Decoder. In terms …
A Configurable Decoder For Pin-Limited Applications, Matthew Collin Jordan
A Configurable Decoder For Pin-Limited Applications, Matthew Collin Jordan
LSU Master's Theses
Pin limitation is the restriction imposed on an IC chip by the unavailability of a sufficient number of I/O pins. This impacts the design and performance of the chip, as the amount of information that can be passed through the boundary of the chip becomes limited. One area that would benefit from a reduction of the effect of pin limitation is reconfigurable architectures. In this work, we consider reconfigurable devices called Field Programmable Gate Arrays (FPGAs). Due to pin limitation, current FPGAs use a form of 1-hot decoder to select elements (one frame at a time) during partial reconfiguration. This …
Designing Switches For Routing In Circuit-Switched Trees, Dinesh Prasad Venkat Rao
Designing Switches For Routing In Circuit-Switched Trees, Dinesh Prasad Venkat Rao
LSU Master's Theses
Reconfigurable computing provides a fast and flexible solution for intensive computing processes. Thus, it acts as a bridge between software controlled and hardware based processors. The self–reconfigurable gate array (SRGA) is a reconfigurable architecture that allows fast switching between operations on a reconfigurable device. It consists of a 2-dimensional array of processing elements (PEs) connected using a binary tree structure, called a circuit-switched tree (CST). A CST is a balanced binary tree in which leaves represent processing elements (PE) and internal nodes represent switches. The PEs in the CST communicates with each other by configuring the appropriate switches in the …