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Electrical and Computer Engineering

Louisiana State University

Theses/Dissertations

CMOS

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Full-Text Articles in Engineering

Phase Noise Analyses And Measurements In The Hybrid Memristor-Cmos Phase-Locked Loop Design And Devices Beyond Bulk Cmos, Naheem Olakunle Adesina Mar 2022

Phase Noise Analyses And Measurements In The Hybrid Memristor-Cmos Phase-Locked Loop Design And Devices Beyond Bulk Cmos, Naheem Olakunle Adesina

LSU Doctoral Dissertations

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.

Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, …


5-Bit Dual-Slope Analog-To-Digital Converter-Based Time-To-Digital Converter Chip Design In Cmos Technology, Jojoe S. Sagoe Nov 2019

5-Bit Dual-Slope Analog-To-Digital Converter-Based Time-To-Digital Converter Chip Design In Cmos Technology, Jojoe S. Sagoe

LSU Master's Theses

Time-to-Digital Converters (TDC) have gained increasing importance in modern implementations of mixed-signal, data-acquisition and processing interfaces and are used to perform high precision time intervals in systems that incorporate Time-of-Flight (ToF) or Time-of-Arrival (ToA) measurements. The linearity of TDCs is very crucial since most Digital Signal Processing (DSP) systems require very linear inputs to achieve high accuracy.

In this work, a TDC has been designed in the 0.5 μm n-well CMOS process that can be used for on-chip integration and in applications requiring high linearity. This TDC used a Dual-Slope-ADC-based architecture for the time-to-digital conversion and consists of the following …


Design Of Cmos Lc Voltage Controlled Oscillators, Chetan Shambhulinga Salimath Jan 2006

Design Of Cmos Lc Voltage Controlled Oscillators, Chetan Shambhulinga Salimath

LSU Master's Theses

This work presents the design and implementation of CMOS LC voltage controlled oscillators. On-chip planar spiral inductors and PMOS inversion mode varactors were utilized to implement the resonator. Two voltage controlled oscillators (VCOs) were realized as a part of this work, one designed to operate at 1.1 GHz while the second at 1.8 GHz. Both VCOs were implemented in a scalable digital CMOS process, with the former in a 1.5 micron CMOS process and the latter in a 0.5 micron technology. A simulation based methodology was adopted to arrive at a simple pi model used to model the metal and …


Techniques For Low Power Analog, Digital And Mixed Signal Cmos Integrated Circuit Design, Chuang Zhang Jan 2005

Techniques For Low Power Analog, Digital And Mixed Signal Cmos Integrated Circuit Design, Chuang Zhang

LSU Doctoral Dissertations

With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low power is becoming increasingly important in integrated circuits. The low power design can increase operation time and/or utilize a smaller size and lighter-weight battery. In this dissertation, several low power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in detail and used to designing an ultra-low power CMOS operational amplifier for operation at …


Ternary Logic To Binary Bit Conversion Using Multiple Input Floating Gate Mosfets In 0.5 Micron N-Well Cmos Technology, Sowmya Subramanian Jan 2005

Ternary Logic To Binary Bit Conversion Using Multiple Input Floating Gate Mosfets In 0.5 Micron N-Well Cmos Technology, Sowmya Subramanian

LSU Master's Theses

In the present work, a CMOS ternary to binary bit conversion technique has been proposed using multiple input floating gate MOSFETs. The proposed circuit has been implemented in 0.5 µm n-well CMOS technology. The ternary input signals of {-1, 0, +1} are represented as -3 V, 0 V and +3 V, respectively. The ternary input is given as a combination of any two of the three voltage levels and the 4-bit binary output is generated in which the left most bit is sign bit (SB) followed by most significant bit (MSB), second significant bit (SSB) and the least significant bit …